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-rw-r--r--llvm/lib/CodeGen/AggressiveAntiDepBreaker.h3
-rw-r--r--llvm/lib/CodeGen/InterferenceCache.h20
-rw-r--r--llvm/lib/CodeGen/LiveRangeCalc.h7
-rw-r--r--llvm/lib/CodeGen/RegAllocBase.h3
-rw-r--r--llvm/lib/CodeGen/RegisterCoalescer.h4
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h2
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h26
-rw-r--r--llvm/lib/CodeGen/SpillPlacement.h2
-rw-r--r--llvm/lib/CodeGen/SplitKit.h2
9 files changed, 37 insertions, 32 deletions
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
index 29b6a108670..2ab9d89574e 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h
@@ -170,7 +170,8 @@ class RegisterClassInfo;
void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag,
- const char *header =NULL, const char *footer =NULL);
+ const char *header = nullptr,
+ const char *footer = nullptr);
void PrescanInstruction(MachineInstr *MI, unsigned Count,
std::set<unsigned>& PassthruRegs);
diff --git a/llvm/lib/CodeGen/InterferenceCache.h b/llvm/lib/CodeGen/InterferenceCache.h
index d3482d0f3a9..91a1da94fba 100644
--- a/llvm/lib/CodeGen/InterferenceCache.h
+++ b/llvm/lib/CodeGen/InterferenceCache.h
@@ -77,7 +77,8 @@ class InterferenceCache {
/// Iterator pointing into the fixed RegUnit interference.
LiveInterval::iterator FixedI;
- RegUnitInfo(LiveIntervalUnion &LIU) : VirtTag(LIU.getTag()), Fixed(0) {
+ RegUnitInfo(LiveIntervalUnion &LIU)
+ : VirtTag(LIU.getTag()), Fixed(nullptr) {
VirtI.setMap(LIU.getMap());
}
};
@@ -93,7 +94,7 @@ class InterferenceCache {
void update(unsigned MBBNum);
public:
- Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
+ Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {}
void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
assert(!hasRefs() && "Cannot clear cache entry with references");
@@ -148,8 +149,9 @@ class InterferenceCache {
Entry *get(unsigned PhysReg);
public:
- InterferenceCache() : TRI(0), LIUArray(0), MF(0), PhysRegEntries(NULL),
- PhysRegEntriesCount(0), RoundRobin(0) {}
+ InterferenceCache()
+ : TRI(nullptr), LIUArray(nullptr), MF(nullptr), PhysRegEntries(nullptr),
+ PhysRegEntriesCount(0), RoundRobin(0) {}
~InterferenceCache() {
free(PhysRegEntries);
@@ -172,7 +174,7 @@ public:
static BlockInterference NoInterference;
void setEntry(Entry *E) {
- Current = 0;
+ Current = nullptr;
// Update reference counts. Nothing happens when RefCount reaches 0, so
// we don't have to check for E == CacheEntry etc.
if (CacheEntry)
@@ -184,10 +186,10 @@ public:
public:
/// Cursor - Create a dangling cursor.
- Cursor() : CacheEntry(0), Current(0) {}
- ~Cursor() { setEntry(0); }
+ Cursor() : CacheEntry(nullptr), Current(nullptr) {}
+ ~Cursor() { setEntry(nullptr); }
- Cursor(const Cursor &O) : CacheEntry(0), Current(0) {
+ Cursor(const Cursor &O) : CacheEntry(nullptr), Current(nullptr) {
setEntry(O.CacheEntry);
}
@@ -200,7 +202,7 @@ public:
void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) {
// Release reference before getting a new one. That guarantees we can
// actually have CacheEntries live cursors.
- setEntry(0);
+ setEntry(nullptr);
if (PhysReg)
setEntry(Cache.get(PhysReg));
}
diff --git a/llvm/lib/CodeGen/LiveRangeCalc.h b/llvm/lib/CodeGen/LiveRangeCalc.h
index a3a3fbbed2b..67ab5596d29 100644
--- a/llvm/lib/CodeGen/LiveRangeCalc.h
+++ b/llvm/lib/CodeGen/LiveRangeCalc.h
@@ -92,7 +92,7 @@ class LiveRangeCalc {
VNInfo *Value;
LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill)
- : LR(LR), DomNode(node), Kill(kill), Value(0) {}
+ : LR(LR), DomNode(node), Kill(kill), Value(nullptr) {}
};
/// LiveIn - Work list of blocks where the live-in value has yet to be
@@ -125,7 +125,8 @@ class LiveRangeCalc {
void updateLiveIns();
public:
- LiveRangeCalc() : MF(0), MRI(0), Indexes(0), DomTree(0), Alloc(0) {}
+ LiveRangeCalc() : MF(nullptr), MRI(nullptr), Indexes(nullptr),
+ DomTree(nullptr), Alloc(nullptr) {}
//===--------------------------------------------------------------------===//
// High-level interface.
@@ -203,7 +204,7 @@ public:
/// addLiveInBlock().
void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI) {
Seen.set(MBB->getNumber());
- LiveOut[MBB] = LiveOutPair(VNI, (MachineDomTreeNode *)0);
+ LiveOut[MBB] = LiveOutPair(VNI, nullptr);
}
/// addLiveInBlock - Add a block with an unknown live-in value. This
diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h
index 68bd4b5b631..b333c36bff9 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/lib/CodeGen/RegAllocBase.h
@@ -65,7 +65,8 @@ protected:
LiveRegMatrix *Matrix;
RegisterClassInfo RegClassInfo;
- RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
+ RegAllocBase()
+ : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
virtual ~RegAllocBase() {}
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.h b/llvm/lib/CodeGen/RegisterCoalescer.h
index 47c3df14606..e57ceab37d0 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.h
+++ b/llvm/lib/CodeGen/RegisterCoalescer.h
@@ -61,14 +61,14 @@ namespace llvm {
public:
CoalescerPair(const TargetRegisterInfo &tri)
: TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
- Partial(false), CrossClass(false), Flipped(false), NewRC(0) {}
+ Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {}
/// Create a CoalescerPair representing a virtreg-to-physreg copy.
/// No need to call setRegisters().
CoalescerPair(unsigned VirtReg, unsigned PhysReg,
const TargetRegisterInfo &tri)
: TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
- Partial(false), CrossClass(false), Flipped(false), NewRC(0) {}
+ Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {}
/// setRegisters - set registers to match the copy instruction MI. Return
/// false if MI is not a coalescable copy instruction.
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
index 5e11dbb5fb8..39ebadf3011 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
@@ -139,7 +139,7 @@ namespace llvm {
public:
RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
- bool IsValid() const { return Node != NULL; }
+ bool IsValid() const { return Node != nullptr; }
MVT GetValue() const {
assert(IsValid() && "bad iterator");
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index 66835bf5575..290d83a608e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -96,7 +96,7 @@ class SelectionDAGBuilder {
DebugLoc dl;
unsigned SDNodeOrder;
public:
- DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
+ DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
DI(di), dl(DL), SDNodeOrder(SDNO) { }
const DbgValueInst* getDI() { return DI; }
@@ -135,7 +135,7 @@ private:
MachineBasicBlock* BB;
uint32_t ExtraWeight;
- Case() : Low(0), High(0), BB(0), ExtraWeight(0) { }
+ Case() : Low(nullptr), High(nullptr), BB(nullptr), ExtraWeight(0) { }
Case(const Constant *low, const Constant *high, MachineBasicBlock *bb,
uint32_t extraweight) : Low(low), High(high), BB(bb),
ExtraWeight(extraweight) { }
@@ -396,8 +396,8 @@ private:
/// the same function, use the same failure basic block).
class StackProtectorDescriptor {
public:
- StackProtectorDescriptor() : ParentMBB(0), SuccessMBB(0), FailureMBB(0),
- Guard(0) { }
+ StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
+ FailureMBB(nullptr), Guard(nullptr) { }
~StackProtectorDescriptor() { }
/// Returns true if all fields of the stack protector descriptor are
@@ -432,8 +432,8 @@ private:
/// parent mbb after we create the stack protector check (SuccessMBB). This
/// BB is visited only on stack protector check success.
void resetPerBBState() {
- ParentMBB = 0;
- SuccessMBB = 0;
+ ParentMBB = nullptr;
+ SuccessMBB = nullptr;
}
/// Reset state that only changes when we switch functions.
@@ -446,8 +446,8 @@ private:
/// 2.The guard variable since the guard variable we are checking against is
/// always the same.
void resetPerFunctionState() {
- FailureMBB = 0;
- Guard = 0;
+ FailureMBB = nullptr;
+ Guard = nullptr;
}
MachineBasicBlock *getParentMBB() { return ParentMBB; }
@@ -482,7 +482,7 @@ private:
/// block will be created.
MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
MachineBasicBlock *ParentMBB,
- MachineBasicBlock *SuccMBB = 0);
+ MachineBasicBlock *SuccMBB = nullptr);
};
private:
@@ -538,7 +538,7 @@ public:
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
CodeGenOpt::Level ol)
- : CurInst(NULL), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
+ : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
HasTailCall(false) {
}
@@ -600,13 +600,13 @@ public:
void setValue(const Value *V, SDValue NewN) {
SDValue &N = NodeMap[V];
- assert(N.getNode() == 0 && "Already set a value for this node!");
+ assert(!N.getNode() && "Already set a value for this node!");
N = NewN;
}
void setUnusedArgValue(const Value *V, SDValue NewN) {
SDValue &N = UnusedArgNodeMap[V];
- assert(N.getNode() == 0 && "Already set a value for this node!");
+ assert(!N.getNode() && "Already set a value for this node!");
N = NewN;
}
@@ -624,7 +624,7 @@ public:
void CopyToExportRegsIfNeeded(const Value *V);
void ExportFromCurrentBlock(const Value *V);
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
- MachineBasicBlock *LandingPad = NULL);
+ MachineBasicBlock *LandingPad = nullptr);
std::pair<SDValue, SDValue> LowerCallOperands(const CallInst &CI,
unsigned ArgIdx,
diff --git a/llvm/lib/CodeGen/SpillPlacement.h b/llvm/lib/CodeGen/SpillPlacement.h
index a88d7ac7391..43fc7f50cef 100644
--- a/llvm/lib/CodeGen/SpillPlacement.h
+++ b/llvm/lib/CodeGen/SpillPlacement.h
@@ -65,7 +65,7 @@ class SpillPlacement : public MachineFunctionPass {
public:
static char ID; // Pass identification, replacement for typeid.
- SpillPlacement() : MachineFunctionPass(ID), nodes(0) {}
+ SpillPlacement() : MachineFunctionPass(ID), nodes(nullptr) {}
~SpillPlacement() { releaseMemory(); }
/// BorderConstraint - A basic block has separate constraints for entry and
diff --git a/llvm/lib/CodeGen/SplitKit.h b/llvm/lib/CodeGen/SplitKit.h
index f029c73d122..08bcf35350d 100644
--- a/llvm/lib/CodeGen/SplitKit.h
+++ b/llvm/lib/CodeGen/SplitKit.h
@@ -417,7 +417,7 @@ public:
/// @param LRMap When not null, this vector will map each live range in Edit
/// back to the indices returned by openIntv.
/// There may be extra indices created by dead code elimination.
- void finish(SmallVectorImpl<unsigned> *LRMap = 0);
+ void finish(SmallVectorImpl<unsigned> *LRMap = nullptr);
/// dump - print the current interval maping to dbgs().
void dump() const;
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