diff options
Diffstat (limited to 'llvm/lib/CodeGen')
23 files changed, 276 insertions, 267 deletions
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index 162e04fe4ce..ffcb9a09ad7 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -448,11 +448,11 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, // FIXME: The issue with predicated instruction is more complex. We are being // conservatively here because the kill markers cannot be trusted after // if-conversion: - // %r6<def> = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] + // %r6 = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] // ... - // STR %r0, %r6<kill>, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395] - // %r6<def> = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12] - // STR %r0, %r6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) + // STR %r0, killed %r6, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395] + // %r6 = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12] + // STR %r0, killed %r6, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) // // The first R6 kill is not really a kill since it's killed by a predicated // instruction which may not be executed. The second R6 def may or may not diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 1bc8b4eee0f..f1459d9d0a1 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -815,10 +815,8 @@ static void emitKill(const MachineInstr *MI, AsmPrinter &AP) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &Op = MI->getOperand(i); assert(Op.isReg() && "KILL instruction must have only register operands"); - OS << ' ' - << printReg(Op.getReg(), - AP.MF->getSubtarget().getRegisterInfo()) - << (Op.isDef() ? "<def>" : "<kill>"); + OS << ' ' << (Op.isDef() ? "def " : "killed ") + << printReg(Op.getReg(), AP.MF->getSubtarget().getRegisterInfo()); } AP.OutStreamer->AddComment(OS.str()); AP.OutStreamer->AddBlankLine(); diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp index 92e73cb502c..99270ff4ea7 100644 --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -1968,7 +1968,7 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) { // // BB2: // r1 = op2, ... - // = op3, r1<kill> + // = op3, killed r1 IsSafe = false; break; } diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp index 30918a98be0..98e22b24d37 100644 --- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -170,11 +170,11 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) { // FIXME: The issue with predicated instruction is more complex. We are being // conservative here because the kill markers cannot be trusted after // if-conversion: - // %r6<def> = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] + // %r6 = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] // ... - // STR %r0, %r6<kill>, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395] - // %r6<def> = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12] - // STR %r0, %r6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) + // STR %r0, killed %r6, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395] + // %r6 = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12] + // STR %r0, killed %r6, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) // // The first R6 kill is not really a kill since it's killed by a predicated // instruction which may not be executed. The second R6 def may or may not diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp index dc5040471f3..6ef97d6dd5e 100644 --- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp +++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp @@ -104,7 +104,7 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { if (DstSubReg == InsReg) { // No need to insert an identity copy instruction. // Watch out for case like this: - // %rax<def> = SUBREG_TO_REG 0, %eax<kill>, 3 + // %rax = SUBREG_TO_REG 0, killed %eax, 3 // We must leave %rax live. if (DstReg != InsReg) { MI->setDesc(TII->get(TargetOpcode::KILL)); diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp index 1962b4ca65d..308b6d293d3 100644 --- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp +++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp @@ -421,7 +421,7 @@ bool ImplicitNullChecks::canHoistInst(MachineInstr *FaultingMI, // test %rcx, %rcx // je _null_block // _non_null_block: - // %rdx<def> = INST + // %rdx = INST // ... // // This restriction does not apply to the faulting load inst because in diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index aff6189283e..56f5a0c047c 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -360,7 +360,7 @@ bool InlineSpiller::isSibling(unsigned Reg) { /// /// x = def /// spill x -/// y = use x<kill> +/// y = use killed x /// /// This hoist only helps when the copy kills its source. /// diff --git a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp index 06807542b34..d181fe83b88 100644 --- a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -700,7 +700,7 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) { // // %eax = COPY %5 // FOO %5 <--- MI, cancel kill because %eax is live. - // BAR %eax<kill> + // BAR killed %eax // // There should be no kill flag on FOO when %5 is rewritten as %eax. for (auto &RUP : RU) { @@ -721,7 +721,7 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) { // Example: // %1 = ... ; R32: %1 // %2:high16 = ... ; R64: %2 - // = read %2<kill> ; R64: %2 + // = read killed %2 ; R64: %2 // = read %1 ; R32: %1 // The <kill> flag is correct for %2, but the register allocator may // assign R0L to %1, and R0 to %2 because the low 32bits of R0 diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp index f9c5652e8a1..1c2bbc3df02 100644 --- a/llvm/lib/CodeGen/LiveVariables.cpp +++ b/llvm/lib/CodeGen/LiveVariables.cpp @@ -235,7 +235,7 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { // Otherwise, the last sub-register def implicitly defines this register. // e.g. // AH = - // AL = ... <imp-def EAX>, <imp-kill AH> + // AL = ... implicit-def EAX, implicit killed AH // = AH // ... // = EAX @@ -321,17 +321,17 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) { // AH = // // = AX - // = AL, AX<imp-use, kill> + // = AL, implicit killed AX // AX = // // Or whole register is defined, but not used at all. - // AX<dead> = + // dead AX = // ... // AX = // // Or whole register is defined, but only partly used. - // AX<dead> = AL<imp-def> - // = AL<kill> + // dead AX = implicit-def AL + // = killed AL // AX = MachineInstr *LastPartDef = nullptr; unsigned LastPartDefDist = 0; @@ -364,7 +364,7 @@ bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) { if (!PhysRegUse[Reg]) { // Partial uses. Mark register def dead and add implicit def of // sub-registers which are used. - // EAX<dead> = op AL<imp-def> + // dead EAX = op implicit-def AL // That is, EAX def is dead but AL def extends pass it. PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index aa0f38036b1..e8a358e5209 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -164,7 +164,7 @@ public: void printTargetFlags(const MachineOperand &Op); void print(const MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies, - LLT TypeToPrint, bool IsDef = false); + LLT TypeToPrint, bool PrintDef = true); void print(const LLVMContext &Context, const TargetInstrInfo &TII, const MachineMemOperand &Op); void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID); @@ -257,25 +257,11 @@ static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, OS << ')'; } -static void printRegClassOrBank(unsigned Reg, raw_ostream &OS, - const MachineRegisterInfo &RegInfo, - const TargetRegisterInfo *TRI) { - if (RegInfo.getRegClassOrNull(Reg)) - OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); - else if (RegInfo.getRegBankOrNull(Reg)) - OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); - else { - OS << "_"; - assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && - "Generic registers must have a valid type"); - } -} - static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI) { raw_string_ostream OS(Dest.Value); - printRegClassOrBank(Reg, OS, RegInfo, TRI); + OS << printRegClassOrBank(Reg, RegInfo, TRI); } @@ -289,7 +275,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, unsigned Reg = TargetRegisterInfo::index2VirtReg(I); yaml::VirtualRegisterDefinition VReg; VReg.ID = I; - printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); + ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); unsigned PreferredReg = RegInfo.getSimpleHint(Reg); if (PreferredReg) printRegMIR(PreferredReg, VReg.PreferredRegister, TRI); @@ -661,44 +647,6 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { OS.indent(2) << "}\n"; } -/// Return true when an instruction has tied register that can't be determined -/// by the instruction's descriptor. -static bool hasComplexRegisterTies(const MachineInstr &MI) { - const MCInstrDesc &MCID = MI.getDesc(); - for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) { - const auto &Operand = MI.getOperand(I); - if (!Operand.isReg() || Operand.isDef()) - // Ignore the defined registers as MCID marks only the uses as tied. - continue; - int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); - int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1; - if (ExpectedTiedIdx != TiedIdx) - return true; - } - return false; -} - -static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx, - SmallBitVector &PrintedTypes, - const MachineRegisterInfo &MRI) { - const MachineOperand &Op = MI.getOperand(OpIdx); - if (!Op.isReg()) - return LLT{}; - - if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands()) - return MRI.getType(Op.getReg()); - - auto &OpInfo = MI.getDesc().OpInfo[OpIdx]; - if (!OpInfo.isGenericType()) - return MRI.getType(Op.getReg()); - - if (PrintedTypes[OpInfo.getGenericTypeIndex()]) - return LLT{}; - - PrintedTypes.set(OpInfo.getGenericTypeIndex()); - return MRI.getType(Op.getReg()); -} - void MIPrinter::print(const MachineInstr &MI) { const auto *MF = MI.getMF(); const auto &MRI = MF->getRegInfo(); @@ -711,7 +659,7 @@ void MIPrinter::print(const MachineInstr &MI) { assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); SmallBitVector PrintedTypes(8); - bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI); + bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies(); unsigned I = 0, E = MI.getNumOperands(); for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && !MI.getOperand(I).isImplicit(); @@ -719,8 +667,8 @@ void MIPrinter::print(const MachineInstr &MI) { if (I) OS << ", "; print(MI, I, TRI, ShouldPrintRegisterTies, - getTypeToPrint(MI, I, PrintedTypes, MRI), - /*IsDef=*/true); + MI.getTypeToPrint(I, PrintedTypes, MRI), + /*PrintDef=*/false); } if (I) @@ -736,7 +684,7 @@ void MIPrinter::print(const MachineInstr &MI) { if (NeedComma) OS << ", "; print(MI, I, TRI, ShouldPrintRegisterTies, - getTypeToPrint(MI, I, PrintedTypes, MRI)); + MI.getTypeToPrint(I, PrintedTypes, MRI)); NeedComma = true; } @@ -902,44 +850,17 @@ static const char *getTargetIndexName(const MachineFunction &MF, int Index) { void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies, LLT TypeToPrint, - bool IsDef) { + bool PrintDef) { const MachineOperand &Op = MI.getOperand(OpIdx); printTargetFlags(Op); switch (Op.getType()) { case MachineOperand::MO_Register: { - unsigned Reg = Op.getReg(); - if (Op.isImplicit()) - OS << (Op.isDef() ? "implicit-def " : "implicit "); - else if (!IsDef && Op.isDef()) - // Print the 'def' flag only when the operand is defined after '='. - OS << "def "; - if (Op.isInternalRead()) - OS << "internal "; - if (Op.isDead()) - OS << "dead "; - if (Op.isKill()) - OS << "killed "; - if (Op.isUndef()) - OS << "undef "; - if (Op.isEarlyClobber()) - OS << "early-clobber "; - if (Op.isDebug()) - OS << "debug-use "; - OS << printReg(Reg, TRI); - // Print the sub register. - if (Op.getSubReg() != 0) - OS << '.' << TRI->getSubRegIndexName(Op.getSubReg()); - if (TargetRegisterInfo::isVirtualRegister(Reg)) { - const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo(); - if (IsDef || MRI.def_empty(Reg)) { - OS << ':'; - printRegClassOrBank(Reg, OS, MRI, TRI); - } - } + unsigned TiedOperandIdx = 0; if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef()) - OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(OpIdx) << ")"; - if (TypeToPrint.isValid()) - OS << '(' << TypeToPrint << ')'; + TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx); + const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo(); + Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies, + TiedOperandIdx, TRI, TII); break; } case MachineOperand::MO_Immediate: diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index d26d53d87ca..da63b41858e 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -623,10 +623,10 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) { // Go through implicit defs of CSMI and MI, and clear the kill flags on // their uses in all the instructions between CSMI and MI. // We might have made some of the kill flags redundant, consider: - // subs ... %nzcv<imp-def> <- CSMI - // csinc ... %nzcv<imp-use,kill> <- this kill flag isn't valid anymore - // subs ... %nzcv<imp-def> <- MI, to be eliminated - // csinc ... %nzcv<imp-use,kill> + // subs ... implicit-def %nzcv <- CSMI + // csinc ... implicit killed %nzcv <- this kill flag isn't valid anymore + // subs ... implicit-def %nzcv <- MI, to be eliminated + // csinc ... implicit killed %nzcv // Since we eliminated MI, and reused a register imp-def'd by CSMI // (here %nzcv), that register, if it was killed before MI, should have // that kill flag removed, because it's lifetime was extended. diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index 1590b205def..8b4f9970b22 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -226,19 +226,19 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) { // The two copies cancel out and the source of the first copy // hasn't been overridden, eliminate the second one. e.g. - // %ecx<def> = COPY %eax + // %ecx = COPY %eax // ... nothing clobbered eax. - // %eax<def> = COPY %ecx + // %eax = COPY %ecx // => - // %ecx<def> = COPY %eax + // %ecx = COPY %eax // // or // - // %ecx<def> = COPY %eax + // %ecx = COPY %eax // ... nothing clobbered eax. - // %ecx<def> = COPY %eax + // %ecx = COPY %eax // => - // %ecx<def> = COPY %eax + // %ecx = COPY %eax if (eraseIfRedundant(*MI, Def, Src) || eraseIfRedundant(*MI, Src, Def)) continue; @@ -262,11 +262,11 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) { // If 'Def' is previously source of another copy, then this earlier copy's // source is no longer available. e.g. - // %xmm9<def> = copy %xmm2 + // %xmm9 = copy %xmm2 // ... - // %xmm2<def> = copy %xmm0 + // %xmm2 = copy %xmm0 // ... - // %xmm2<def> = copy %xmm9 + // %xmm2 = copy %xmm9 ClobberRegister(Def); for (const MachineOperand &MO : MI->implicit_operands()) { if (!MO.isReg() || !MO.isDef()) diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 8bdc183fabb..464df33e6be 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -18,6 +18,7 @@ #include "llvm/ADT/Hashing.h" #include "llvm/ADT/None.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Analysis/AliasAnalysis.h" @@ -742,7 +743,7 @@ MachineInstr::readsWritesVirtualRegister(unsigned Reg, if (MO.isUse()) Use |= !MO.isUndef(); else if (MO.getSubReg() && !MO.isUndef()) - // A partial <def,undef> doesn't count as reading the register. + // A partial def undef doesn't count as reading the register. PartDef = true; else FullDef = true; @@ -1163,6 +1164,41 @@ void MachineInstr::copyImplicitOps(MachineFunction &MF, } } +bool MachineInstr::hasComplexRegisterTies() const { + const MCInstrDesc &MCID = getDesc(); + for (unsigned I = 0, E = getNumOperands(); I < E; ++I) { + const auto &Operand = getOperand(I); + if (!Operand.isReg() || Operand.isDef()) + // Ignore the defined registers as MCID marks only the uses as tied. + continue; + int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); + int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1; + if (ExpectedTiedIdx != TiedIdx) + return true; + } + return false; +} + +LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, + const MachineRegisterInfo &MRI) const { + const MachineOperand &Op = getOperand(OpIdx); + if (!Op.isReg()) + return LLT{}; + + if (isVariadic() || OpIdx >= getNumExplicitOperands()) + return MRI.getType(Op.getReg()); + + auto &OpInfo = getDesc().OpInfo[OpIdx]; + if (!OpInfo.isGenericType()) + return MRI.getType(Op.getReg()); + + if (PrintedTypes[OpInfo.getGenericTypeIndex()]) + return LLT{}; + + PrintedTypes.set(OpInfo.getGenericTypeIndex()); + return MRI.getType(Op.getReg()); +} + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVM_DUMP_METHOD void MachineInstr::dump() const { dbgs() << " "; @@ -1204,21 +1240,31 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, // Save a list of virtual registers. SmallVector<unsigned, 8> VirtRegs; + SmallBitVector PrintedTypes(8); + bool ShouldPrintRegisterTies = hasComplexRegisterTies(); + auto getTiedOperandIdx = [&](unsigned OpIdx) { + if (!ShouldPrintRegisterTies) + return 0U; + const MachineOperand &MO = getOperand(OpIdx); + if (MO.isReg() && MO.isTied() && !MO.isDef()) + return findTiedOperandIdx(OpIdx); + return 0U; + }; // Print explicitly defined operands on the left of an assignment syntax. unsigned StartOp = 0, e = getNumOperands(); for (; StartOp < e && getOperand(StartOp).isReg() && - getOperand(StartOp).isDef() && - !getOperand(StartOp).isImplicit(); + getOperand(StartOp).isDef() && !getOperand(StartOp).isImplicit(); ++StartOp) { - if (StartOp != 0) OS << ", "; - getOperand(StartOp).print(OS, MST, TRI, IntrinsicInfo); + if (StartOp != 0) + OS << ", "; + LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{}; + unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); + getOperand(StartOp).print(OS, MST, TypeToPrint, /*PrintDef=*/false, + ShouldPrintRegisterTies, TiedOperandIdx, TRI, + IntrinsicInfo); unsigned Reg = getOperand(StartOp).getReg(); - if (TargetRegisterInfo::isVirtualRegister(Reg)) { + if (TargetRegisterInfo::isVirtualRegister(Reg)) VirtRegs.push_back(Reg); - LLT Ty = MRI ? MRI->getType(Reg) : LLT{}; - if (Ty.isValid()) - OS << '(' << Ty << ')'; - } } if (StartOp != 0) @@ -1241,7 +1287,12 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { // Print asm string. OS << " "; - getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI); + const unsigned OpIdx = InlineAsm::MIOp_AsmString; + LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{}; + unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); + getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, + ShouldPrintRegisterTies, TiedOperandIdx, TRI, + IntrinsicInfo); // Print HasSideEffects, MayLoad, MayStore, IsAlignStack unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); @@ -1284,8 +1335,12 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata()); if (DIV && !DIV->getName().empty()) OS << "!\"" << DIV->getName() << '\"'; - else - MO.print(OS, MST, TRI); + else { + LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; + unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); + MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, + ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); + } } else if (TRI && (isInsertSubreg() || isRegSequence() || (isSubregToReg() && i == 3)) && MO.isImm()) { OS << TRI->getSubRegIndexName(MO.getImm()); @@ -1347,8 +1402,12 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, // Compute the index of the next operand descriptor. AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); - } else - MO.print(OS, MST, TRI); + } else { + LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; + unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); + MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, ShouldPrintRegisterTies, + TiedOperandIdx, TRI, IntrinsicInfo); + } } bool HaveSemi = false; diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp index def4d682dec..f5857db8ada 100644 --- a/llvm/lib/CodeGen/MachineOperand.cpp +++ b/llvm/lib/CodeGen/MachineOperand.cpp @@ -15,10 +15,11 @@ #include "llvm/Analysis/Loads.h" #include "llvm/CodeGen/MIRPrinter.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/IR/Constants.h" #include "llvm/IR/ModuleSlotTracker.h" +#include "llvm/Target/TargetIntrinsicInfo.h" +#include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -333,75 +334,86 @@ hash_code llvm::hash_value(const MachineOperand &MO) { llvm_unreachable("Invalid machine operand type"); } +// Try to crawl up to the machine function and get TRI and IntrinsicInfo from +// it. +static void tryToGetTargetInfo(const MachineOperand &MO, + const TargetRegisterInfo *&TRI, + const TargetIntrinsicInfo *&IntrinsicInfo) { + if (const MachineInstr *MI = MO.getParent()) { + if (const MachineBasicBlock *MBB = MI->getParent()) { + if (const MachineFunction *MF = MBB->getParent()) { + TRI = MF->getSubtarget().getRegisterInfo(); + IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); + } + } + } +} + void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI, const TargetIntrinsicInfo *IntrinsicInfo) const { + tryToGetTargetInfo(*this, TRI, IntrinsicInfo); ModuleSlotTracker DummyMST(nullptr); - print(OS, DummyMST, TRI, IntrinsicInfo); + print(OS, DummyMST, LLT{}, /*PrintDef=*/false, + /*ShouldPrintRegisterTies=*/true, + /*TiedOperandIdx=*/0, TRI, IntrinsicInfo); } void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, + LLT TypeToPrint, bool PrintDef, + bool ShouldPrintRegisterTies, + unsigned TiedOperandIdx, const TargetRegisterInfo *TRI, const TargetIntrinsicInfo *IntrinsicInfo) const { switch (getType()) { - case MachineOperand::MO_Register: - OS << printReg(getReg(), TRI, getSubReg()); - - if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || - isInternalRead() || isEarlyClobber() || isTied()) { - OS << '<'; - bool NeedComma = false; - if (isDef()) { - if (NeedComma) - OS << ','; - if (isEarlyClobber()) - OS << "earlyclobber,"; - if (isImplicit()) - OS << "imp-"; - OS << "def"; - NeedComma = true; - // <def,read-undef> only makes sense when getSubReg() is set. - // Don't clutter the output otherwise. - if (isUndef() && getSubReg()) - OS << ",read-undef"; - } else if (isImplicit()) { - OS << "imp-use"; - NeedComma = true; - } - - if (isKill()) { - if (NeedComma) - OS << ','; - OS << "kill"; - NeedComma = true; - } - if (isDead()) { - if (NeedComma) - OS << ','; - OS << "dead"; - NeedComma = true; - } - if (isUndef() && isUse()) { - if (NeedComma) - OS << ','; - OS << "undef"; - NeedComma = true; - } - if (isInternalRead()) { - if (NeedComma) - OS << ','; - OS << "internal"; - NeedComma = true; - } - if (isTied()) { - if (NeedComma) - OS << ','; - OS << "tied"; - if (TiedTo != 15) - OS << unsigned(TiedTo - 1); + case MachineOperand::MO_Register: { + unsigned Reg = getReg(); + if (isImplicit()) + OS << (isDef() ? "implicit-def " : "implicit "); + else if (PrintDef && isDef()) + // Print the 'def' flag only when the operand is defined after '='. + OS << "def "; + if (isInternalRead()) + OS << "internal "; + if (isDead()) + OS << "dead "; + if (isKill()) + OS << "killed "; + if (isUndef()) + OS << "undef "; + if (isEarlyClobber()) + OS << "early-clobber "; + if (isDebug()) + OS << "debug-use "; + OS << printReg(Reg, TRI); + // Print the sub register. + if (unsigned SubReg = getSubReg()) { + if (TRI) + OS << '.' << TRI->getSubRegIndexName(SubReg); + else + OS << ".subreg" << SubReg; + } + // Print the register class / bank. + if (TargetRegisterInfo::isVirtualRegister(Reg)) { + if (const MachineInstr *MI = getParent()) { + if (const MachineBasicBlock *MBB = MI->getParent()) { + if (const MachineFunction *MF = MBB->getParent()) { + const MachineRegisterInfo &MRI = MF->getRegInfo(); + if (!PrintDef || MRI.def_empty(Reg)) { + OS << ':'; + OS << printRegClassOrBank(Reg, MRI, TRI); + } + } + } } - OS << '>'; } + // Print ties. + if (ShouldPrintRegisterTies && isTied() && !isDef()) + OS << "(tied-def " << TiedOperandIdx << ")"; + // Print types. + if (TypeToPrint.isValid()) + OS << '(' << TypeToPrint << ')'; break; + } case MachineOperand::MO_Immediate: OS << getImm(); break; @@ -475,23 +487,27 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << '>'; break; case MachineOperand::MO_RegisterMask: { - unsigned NumRegsInMask = 0; - unsigned NumRegsEmitted = 0; OS << "<regmask"; - for (unsigned i = 0; i < TRI->getNumRegs(); ++i) { - unsigned MaskWord = i / 32; - unsigned MaskBit = i % 32; - if (getRegMask()[MaskWord] & (1 << MaskBit)) { - if (PrintRegMaskNumRegs < 0 || - NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) { - OS << " " << printReg(i, TRI); - NumRegsEmitted++; + if (TRI) { + unsigned NumRegsInMask = 0; + unsigned NumRegsEmitted = 0; + for (unsigned i = 0; i < TRI->getNumRegs(); ++i) { + unsigned MaskWord = i / 32; + unsigned MaskBit = i % 32; + if (getRegMask()[MaskWord] & (1 << MaskBit)) { + if (PrintRegMaskNumRegs < 0 || + NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) { + OS << " " << printReg(i, TRI); + NumRegsEmitted++; + } + NumRegsInMask++; } - NumRegsInMask++; } + if (NumRegsEmitted != NumRegsInMask) + OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more..."; + } else { + OS << " ..."; } - if (NumRegsEmitted != NumRegsInMask) - OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more..."; OS << ">"; break; } diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 7857084c4e6..f932df71cdb 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -246,14 +246,14 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg, // %bb.1: derived from LLVM BB %bb4.preheader // Predecessors according to CFG: %bb.0 // ... - // %reg16385<def> = DEC64_32r %reg16437, %eflags<imp-def,dead> + // %reg16385 = DEC64_32r %reg16437, implicit-def dead %eflags // ... - // JE_4 <%bb.37>, %eflags<imp-use> + // JE_4 <%bb.37>, implicit %eflags // Successors according to CFG: %bb.37 %bb.2 // // %bb.2: derived from LLVM BB %bb.nph // Predecessors according to CFG: %bb.0 %bb.1 - // %reg16386<def> = PHI %reg16434, %bb.0, %reg16385, %bb.1 + // %reg16386 = PHI %reg16434, %bb.0, %reg16385, %bb.1 BreakPHIEdge = true; for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { MachineInstr *UseInst = MO.getParent(); diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 6834059234e..d5658db161a 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1961,7 +1961,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, if (MOI->isDef()) { if (Sub != 0) { hasSubRegDef = true; - // An operand %0:sub0<def> reads %0:sub1..n. Invert the lane + // An operand %0:sub0 reads %0:sub1..n. Invert the lane // mask for subregister defs. Read-undef defs will be handled by // readsReg below. SLM = ~SLM; diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index f26f43d79f2..97011d55d89 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -272,7 +272,7 @@ void RegAllocFast::addKillFlag(const LiveReg &LR) { // subreg of this register and given we don't track which // lanes are actually dead, we cannot insert a kill flag here. // Otherwise we may end up in a situation like this: - // ... = (MO) physreg:sub1, physreg <implicit-use, kill> + // ... = (MO) physreg:sub1, implicit killed physreg // ... <== Here we would allow later pass to reuse physreg:sub1 // which is potentially wrong. // LR:sub0 = ... @@ -675,7 +675,7 @@ RegAllocFast::LiveRegMap::iterator RegAllocFast::reloadVirtReg(MachineInstr &MI, } else if (MO.isKill()) { // We must remove kill flags from uses of reloaded registers because the // register would be killed immediately, and there might be a second use: - // %foo = OR %x<kill>, %x + // %foo = OR killed %x, %x // This would cause a second reload of %x into a different register. DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n"); MO.setIsKill(false); diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 09875d336fd..685271baa4a 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -667,7 +667,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, // its other operand is coalesced to the copy dest register, see if we can // transform the copy into a noop by commuting the definition. For example, // - // A3 = op A2 B0<kill> + // A3 = op A2 killed B0 // ... // B1 = A3 <- this copy // ... @@ -675,7 +675,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, // // ==> // - // B2 = op B0 A2<kill> + // B2 = op B0 killed A2 // ... // B1 = B2 <- now an identity copy // ... @@ -768,7 +768,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, // ... // B = A // ... - // C = A<kill> + // C = killed A // ... // = B @@ -1254,7 +1254,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, // Make sure that the subrange for resultant undef is removed // For example: // %1:sub1<def,read-undef> = LOAD CONSTANT 1 - // %2<def> = COPY %1 + // %2 = COPY %1 // ==> // %2:sub1<def, read-undef> = LOAD CONSTANT 1 // ; Correct but need to remove the subrange for %2:sub0 @@ -1297,7 +1297,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, // = somedef %1 ; %1 GR8 // => // %1 = somedef ; %1 GR8 - // ECX<def, dead> = remat ; CL<imp-def> + // dead ECX = remat ; implicit-def CL // = somedef %1 ; %1 GR8 // %1 will see the inteferences with CL but not with CH since // no live-ranges would have been created for ECX. @@ -1352,7 +1352,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) { // ProcessImpicitDefs may leave some copies of <undef> values, it only removes // local variables. When we have a copy like: // - // %1 = COPY %2<undef> + // %1 = COPY undef %2 // // We delete the copy and remove the corresponding value number from %1. // Any uses of that value number are marked as <undef>. @@ -1927,7 +1927,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { // // %dst:ssub0<def,read-undef> = FOO // %src = BAR -// %dst:ssub1<def> = COPY %src +// %dst:ssub1 = COPY %src // // The live range of %src overlaps the %dst value defined by FOO, but // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane @@ -1942,9 +1942,9 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { // is live, but never read. This can happen because we don't compute // individual live ranges per lane. // -// %dst<def> = FOO +// %dst = FOO // %src = BAR -// %dst:ssub1<def> = COPY %src +// %dst:ssub1 = COPY %src // // This kind of interference is only resolved locally. If the clobbered // lane value escapes the block, the join is aborted. @@ -2287,7 +2287,7 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) { // // This adds ssub1 to the set of valid lanes in %src: // - // %src:ssub1<def> = FOO + // %src:ssub1 = FOO // // This leaves only ssub1 valid, making any other lanes undef: // @@ -2425,9 +2425,9 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) { // // 1 %dst:ssub0 = FOO <-- OtherVNI // 2 %src = BAR <-- VNI - // 3 %dst:ssub1 = COPY %src<kill> <-- Eliminate this copy. - // 4 BAZ %dst<kill> - // 5 QUUX %src<kill> + // 3 %dst:ssub1 = COPY killed %src <-- Eliminate this copy. + // 4 BAZ killed %dst + // 5 QUUX killed %src // // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace // handles this complex value mapping. @@ -2437,7 +2437,7 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) { // If the other live range is killed by DefMI and the live ranges are still // overlapping, it must be because we're looking at an early clobber def: // - // %dst<def,early-clobber> = ASM %src<kill> + // %dst<def,early-clobber> = ASM killed %src // // In this case, it is illegal to merge the two live ranges since the early // clobber def would clobber %src before it was read. @@ -2682,7 +2682,7 @@ void JoinVals::pruneValues(JoinVals &Other, if (!Def.isBlock()) { if (changeInstrs) { // Remove <def,read-undef> flags. This def is now a partial redef. - // Also remove <def,dead> flags since the joined live range will + // Also remove dead flags since the joined live range will // continue past this instruction. for (MachineOperand &MO : Indexes->getInstructionFromIndex(Def)->operands()) { diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index 5aeec854dad..97967124add 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -213,7 +213,7 @@ void RegScavenger::forward() { continue; if (!isRegUsed(Reg)) { // Check if it's partial live: e.g. - // D0 = insert_subreg D0<undef>, S0 + // D0 = insert_subreg undef D0, S0 // ... D0 // The problem is the insert_subreg could be eliminated. The use of // D0 is using a partially undef value. This is not *incorrect* since diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index fc85ea3d166..dade05ce515 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -1379,7 +1379,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) { // for a partially defined original register. For example: // %0:subreg_hireg<def,read-undef> = ... // ... - // %1<def> = COPY %0 + // %1 = COPY %0 if (S.empty()) continue; SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index dfda313f233..f255ba4fef9 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -144,6 +144,21 @@ Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { }); } +Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, + const TargetRegisterInfo *TRI) { + return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { + if (RegInfo.getRegClassOrNull(Reg)) + OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); + else if (RegInfo.getRegBankOrNull(Reg)) + OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); + else { + OS << "_"; + assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && + "Generic registers must have a valid type"); + } + }); +} + } // end namespace llvm /// getAllocatableClass - Return the maximal subclass of the given register diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index c51340766b7..cd4391232c1 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -458,8 +458,8 @@ static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, /// For example, in this code: /// /// %reg1034 = copy %reg1024 -/// %reg1035 = copy %reg1025<kill> -/// %reg1036 = add %reg1034<kill>, %reg1035<kill> +/// %reg1035 = copy killed %reg1025 +/// %reg1036 = add killed %reg1034, killed %reg1035 /// /// %reg1034 is not considered to be killed, since it is copied from a /// register which is not killed. Treating it as not killed lets the @@ -591,31 +591,31 @@ isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC, // general, we want no uses between this instruction and the definition of // the two-address register. // e.g. - // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 - // %reg1029<def> = MOV8rr %reg1028 - // %reg1029<def> = SHR8ri %reg1029, 7, %eflags<imp-def,dead> - // insert => %reg1030<def> = MOV8rr %reg1028 - // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %eflags<imp-def,dead> + // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1 + // %reg1029 = MOV8rr %reg1028 + // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags + // insert => %reg1030 = MOV8rr %reg1028 + // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags // In this case, it might not be possible to coalesce the second MOV8rr // instruction if the first one is coalesced. So it would be profitable to // commute it: - // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 - // %reg1029<def> = MOV8rr %reg1028 - // %reg1029<def> = SHR8ri %reg1029, 7, %eflags<imp-def,dead> - // insert => %reg1030<def> = MOV8rr %reg1029 - // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %eflags<imp-def,dead> + // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1 + // %reg1029 = MOV8rr %reg1028 + // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags + // insert => %reg1030 = MOV8rr %reg1029 + // %reg1030 = ADD8rr killed %reg1029, killed %reg1028, implicit dead %eflags if (!isPlainlyKilled(MI, regC, LIS)) return false; // Ok, we have something like: - // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %eflags<imp-def,dead> + // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags // let's see if it's worth commuting it. // Look for situations like this: - // %reg1024<def> = MOV r1 - // %reg1025<def> = MOV r0 - // %reg1026<def> = ADD %reg1024, %reg1025 + // %reg1024 = MOV r1 + // %reg1025 = MOV r0 + // %reg1026 = ADD %reg1024, %reg1025 // r0 = MOV %reg1026 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy. unsigned ToRegA = getMappedReg(regA, DstRegMap); @@ -713,9 +713,9 @@ bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI, bool TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ // Look for situations like this: - // %reg1024<def> = MOV r1 - // %reg1025<def> = MOV r0 - // %reg1026<def> = ADD %reg1024, %reg1025 + // %reg1024 = MOV r1 + // %reg1025 = MOV r0 + // %reg1026 = ADD %reg1024, %reg1025 // r2 = MOV %reg1026 // Turn ADD into a 3-address instruction to avoid a copy. unsigned FromRegB = getMappedReg(RegB, SrcRegMap); @@ -1466,7 +1466,7 @@ collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) { assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); - // Deal with <undef> uses immediately - simply rewrite the src operand. + // Deal with undef uses immediately - simply rewrite the src operand. if (SrcMO.isUndef() && !DstMO.getSubReg()) { // Constrain the DstReg register class if required. if (TargetRegisterInfo::isVirtualRegister(DstReg)) @@ -1778,8 +1778,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { /// /// Becomes: /// -/// %dst:ssub0<def,undef> = COPY %v1 -/// %dst:ssub1<def> = COPY %v2 +/// undef %dst:ssub0 = COPY %v1 +/// %dst:ssub1 = COPY %v2 void TwoAddressInstructionPass:: eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { MachineInstr &MI = *MBBI; @@ -1803,7 +1803,7 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { MachineOperand &UseMO = MI.getOperand(i); unsigned SrcReg = UseMO.getReg(); unsigned SubIdx = MI.getOperand(i+1).getImm(); - // Nothing needs to be inserted for <undef> operands. + // Nothing needs to be inserted for undef operands. if (UseMO.isUndef()) continue; @@ -1825,7 +1825,7 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { .addReg(DstReg, RegState::Define, SubIdx) .add(UseMO); - // The first def needs an <undef> flag because there is no live register + // The first def needs an undef flag because there is no live register // before it. if (!DefEmitted) { CopyMI->getOperand(0).setIsUndef(true); diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index df950b5d317..6e5674bb8bc 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -380,8 +380,8 @@ void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const { ++NumIdCopies; // Copies like: - // %r0 = COPY %r0<undef> - // %al = COPY %al, %eax<imp-def> + // %r0 = COPY undef %r0 + // %al = COPY %al, implicit-def %eax // give us additional liveness information: The target (super-)register // must not be valid before this point. Replace the COPY with a KILL // instruction to maintain this information. @@ -488,7 +488,7 @@ void VirtRegRewriter::rewrite() { if (SubReg != 0) { if (NoSubRegLiveness) { // A virtual register kill refers to the whole register, so we may - // have to add <imp-use,kill> operands for the super-register. A + // have to add implicit killed operands for the super-register. A // partial redef always kills and redefines the super-register. if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || (MO.isDef() && subRegLiveThrough(*MI, PhysReg))) @@ -513,9 +513,9 @@ void VirtRegRewriter::rewrite() { } } - // The <def,undef> and <def,internal> flags only make sense for + // The def undef and def internal flags only make sense for // sub-register defs, and we are substituting a full physreg. An - // <imp-use,kill> operand from the SuperKills list will represent the + // implicit killed operand from the SuperKills list will represent the // partial read of the super-register. if (MO.isDef()) { MO.setIsUndef(false); |
