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-rw-r--r--llvm/lib/CodeGen/CalcSpillWeights.cpp12
-rw-r--r--llvm/lib/CodeGen/LiveDebugVariables.cpp18
-rw-r--r--llvm/lib/CodeGen/LiveInterval.cpp8
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp6
-rw-r--r--llvm/lib/CodeGen/MachineModuleInfo.cpp3
-rw-r--r--llvm/lib/CodeGen/MachineSink.cpp6
-rw-r--r--llvm/lib/CodeGen/MachineTraceMetrics.cpp12
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.cpp32
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp44
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp6
10 files changed, 93 insertions, 54 deletions
diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp
index 26aa46fb6c2..4877f009cdb 100644
--- a/llvm/lib/CodeGen/CalcSpillWeights.cpp
+++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp
@@ -192,11 +192,15 @@ VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &li) {
// FIXME: we probably shouldn't use floats at all.
volatile float hweight = Hint[hint] += weight;
if (TargetRegisterInfo::isPhysicalRegister(hint)) {
- if (hweight > bestPhys && mri.isAllocatable(hint))
- bestPhys = hweight, hintPhys = hint;
+ if (hweight > bestPhys && mri.isAllocatable(hint)) {
+ bestPhys = hweight;
+ hintPhys = hint;
+ }
} else {
- if (hweight > bestVirt)
- bestVirt = hweight, hintVirt = hint;
+ if (hweight > bestVirt) {
+ bestVirt = hweight;
+ hintVirt = hint;
+ }
}
}
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index e49f8bf9124..0ca267cfafe 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -172,8 +172,10 @@ public:
return L1;
// Splice L2 before L1's members.
UserValue *End = L2;
- while (End->next)
- End->leader = L1, End = End->next;
+ while (End->next) {
+ End->leader = L1;
+ End = End->next;
+ }
End->leader = L1;
End->next = L1->next;
L1->next = L2;
@@ -554,8 +556,10 @@ void UserValue::extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR,
Kills->push_back(Start);
return;
}
- if (Segment->end < Stop)
- Stop = Segment->end, ToEnd = false;
+ if (Segment->end < Stop) {
+ Stop = Segment->end;
+ ToEnd = false;
+ }
}
// There could already be a short def at Start.
@@ -569,8 +573,10 @@ void UserValue::extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR,
}
// Limited by the next def.
- if (I.valid() && I.start() < Stop)
- Stop = I.start(), ToEnd = false;
+ if (I.valid() && I.start() < Stop) {
+ Stop = I.start();
+ ToEnd = false;
+ }
// Limited by VNI's live range.
else if (!ToEnd && Kills)
Kills->push_back(Stop);
diff --git a/llvm/lib/CodeGen/LiveInterval.cpp b/llvm/lib/CodeGen/LiveInterval.cpp
index d80acc0c7f9..e6393200596 100644
--- a/llvm/lib/CodeGen/LiveInterval.cpp
+++ b/llvm/lib/CodeGen/LiveInterval.cpp
@@ -309,10 +309,12 @@ LiveRange::iterator LiveRange::find(SlotIndex Pos) {
size_t Len = size();
do {
size_t Mid = Len >> 1;
- if (Pos < I[Mid].end)
+ if (Pos < I[Mid].end) {
Len = Mid;
- else
- I += Mid + 1, Len -= Mid + 1;
+ } else {
+ I += Mid + 1;
+ Len -= Mid + 1;
+ }
} while (Len);
return I;
}
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 805acb93efd..4103253133e 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1234,8 +1234,10 @@ const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
unsigned MachineInstr::getBundleSize() const {
MachineBasicBlock::const_instr_iterator I = getIterator();
unsigned Size = 0;
- while (I->isBundledWithSucc())
- ++Size, ++I;
+ while (I->isBundledWithSucc()) {
+ ++Size;
+ ++I;
+ }
return Size;
}
diff --git a/llvm/lib/CodeGen/MachineModuleInfo.cpp b/llvm/lib/CodeGen/MachineModuleInfo.cpp
index 1956a701d8e..244e3fbc4e8 100644
--- a/llvm/lib/CodeGen/MachineModuleInfo.cpp
+++ b/llvm/lib/CodeGen/MachineModuleInfo.cpp
@@ -396,7 +396,8 @@ void MachineModuleInfo::TidyLandingPads(DenseMap<MCSymbol*, uintptr_t> *LPMap) {
LandingPad.BeginLabels.erase(LandingPad.BeginLabels.begin() + j);
LandingPad.EndLabels.erase(LandingPad.EndLabels.begin() + j);
- --j, --e;
+ --j;
+ --e;
}
// Remove landing pads with no try-ranges.
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index a10bd7f52e7..b1f3875880b 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -344,8 +344,10 @@ bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
continue;
}
- if (SinkInstruction(MI, SawStore, AllSuccessors))
- ++NumSunk, MadeChange = true;
+ if (SinkInstruction(MI, SawStore, AllSuccessors)) {
+ ++NumSunk;
+ MadeChange = true;
+ }
// If we just processed the first instruction in the block, we're done.
} while (!ProcessedBegin);
diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
index f7edacd5eba..38144593df4 100644
--- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp
+++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
@@ -328,8 +328,10 @@ MinInstrCountEnsemble::pickTracePred(const MachineBasicBlock *MBB) {
continue;
// Pick the predecessor that would give this block the smallest InstrDepth.
unsigned Depth = PredTBI->InstrDepth + CurCount;
- if (!Best || Depth < BestDepth)
- Best = Pred, BestDepth = Depth;
+ if (!Best || Depth < BestDepth) {
+ Best = Pred;
+ BestDepth = Depth;
+ }
}
return Best;
}
@@ -356,8 +358,10 @@ MinInstrCountEnsemble::pickTraceSucc(const MachineBasicBlock *MBB) {
continue;
// Pick the successor that would give this block the smallest InstrHeight.
unsigned Height = SuccTBI->InstrHeight;
- if (!Best || Height < BestHeight)
- Best = Succ, BestHeight = Height;
+ if (!Best || Height < BestHeight) {
+ Best = Succ;
+ BestHeight = Height;
+ }
}
return Best;
}
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 945cb9e2c99..b243d4357bd 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -954,22 +954,28 @@ bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
// Interference for the live-in value.
if (BI.LiveIn) {
- if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
- BC.Entry = SpillPlacement::MustSpill, ++Ins;
- else if (Intf.first() < BI.FirstInstr)
- BC.Entry = SpillPlacement::PrefSpill, ++Ins;
- else if (Intf.first() < BI.LastInstr)
+ if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) {
+ BC.Entry = SpillPlacement::MustSpill;
++Ins;
+ } else if (Intf.first() < BI.FirstInstr) {
+ BC.Entry = SpillPlacement::PrefSpill;
+ ++Ins;
+ } else if (Intf.first() < BI.LastInstr) {
+ ++Ins;
+ }
}
// Interference for the live-out value.
if (BI.LiveOut) {
- if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
- BC.Exit = SpillPlacement::MustSpill, ++Ins;
- else if (Intf.last() > BI.LastInstr)
- BC.Exit = SpillPlacement::PrefSpill, ++Ins;
- else if (Intf.last() > BI.FirstInstr)
+ if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) {
+ BC.Exit = SpillPlacement::MustSpill;
+ ++Ins;
+ } else if (Intf.last() > BI.LastInstr) {
+ BC.Exit = SpillPlacement::PrefSpill;
++Ins;
+ } else if (Intf.last() > BI.FirstInstr) {
+ ++Ins;
+ }
}
// Accumulate the total frequency of inserted spill code.
@@ -1392,8 +1398,10 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg,
if (i == BestCand || !GlobalCand[i].PhysReg)
continue;
unsigned Count = GlobalCand[i].LiveBundles.count();
- if (Count < WorstCount)
- Worst = i, WorstCount = Count;
+ if (Count < WorstCount) {
+ Worst = i;
+ WorstCount = Count;
+ }
}
--NumCands;
GlobalCand[Worst] = GlobalCand[NumCands];
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 73e6c4651a6..79d307a0544 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -677,25 +677,33 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
// now, just use the tightest assertzext/assertsext possible.
bool isSExt = true;
EVT FromVT(MVT::Other);
- if (NumSignBits == RegSize)
- isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
- else if (NumZeroBits >= RegSize-1)
- isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
- else if (NumSignBits > RegSize-8)
- isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
- else if (NumZeroBits >= RegSize-8)
- isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
- else if (NumSignBits > RegSize-16)
- isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
- else if (NumZeroBits >= RegSize-16)
- isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
- else if (NumSignBits > RegSize-32)
- isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
- else if (NumZeroBits >= RegSize-32)
- isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
- else
+ if (NumSignBits == RegSize) {
+ isSExt = true; // ASSERT SEXT 1
+ FromVT = MVT::i1;
+ } else if (NumZeroBits >= RegSize - 1) {
+ isSExt = false; // ASSERT ZEXT 1
+ FromVT = MVT::i1;
+ } else if (NumSignBits > RegSize - 8) {
+ isSExt = true; // ASSERT SEXT 8
+ FromVT = MVT::i8;
+ } else if (NumZeroBits >= RegSize - 8) {
+ isSExt = false; // ASSERT ZEXT 8
+ FromVT = MVT::i8;
+ } else if (NumSignBits > RegSize - 16) {
+ isSExt = true; // ASSERT SEXT 16
+ FromVT = MVT::i16;
+ } else if (NumZeroBits >= RegSize - 16) {
+ isSExt = false; // ASSERT ZEXT 16
+ FromVT = MVT::i16;
+ } else if (NumSignBits > RegSize - 32) {
+ isSExt = true; // ASSERT SEXT 32
+ FromVT = MVT::i32;
+ } else if (NumZeroBits >= RegSize - 32) {
+ isSExt = false; // ASSERT ZEXT 32
+ FromVT = MVT::i32;
+ } else {
continue;
-
+ }
// Add an assertion node.
assert(FromVT != MVT::Other);
Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 39a13c861c7..3881415618e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2268,8 +2268,10 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
}
- if (!C || !GA)
- C = nullptr, GA = nullptr;
+ if (!C || !GA) {
+ C = nullptr;
+ GA = nullptr;
+ }
}
// If we find a valid operand, map to the TargetXXX version so that the
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