diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 | 
3 files changed, 11 insertions, 1 deletions
| diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index bf231d9e526..b0af357b17b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -609,6 +609,7 @@ private:    SDValue WidenVecRes_SIGN_EXTEND_INREG(SDNode* N);    SDValue WidenVecRes_SELECT(SDNode* N);    SDValue WidenVecRes_SELECT_CC(SDNode* N); +  SDValue WidenVecRes_SETCC(SDNode* N);    SDValue WidenVecRes_UNDEF(SDNode *N);    SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);    SDValue WidenVecRes_VSETCC(SDNode* N); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 192cdeee835..bf95bb532f8 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1172,6 +1172,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {    case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;    case ISD::SELECT:            Res = WidenVecRes_SELECT(N); break;    case ISD::SELECT_CC:         Res = WidenVecRes_SELECT_CC(N); break; +  case ISD::SETCC:             Res = WidenVecRes_SETCC(N); break;    case ISD::UNDEF:             Res = WidenVecRes_UNDEF(N); break;    case ISD::VECTOR_SHUFFLE:      Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); @@ -1718,6 +1719,14 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {                       N->getOperand(1), InOp1, InOp2, N->getOperand(4));  } +SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { +  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); +  SDValue InOp1 = GetWidenedVector(N->getOperand(0)); +  SDValue InOp2 = GetWidenedVector(N->getOperand(1)); +  return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, +                     InOp1, InOp2, N->getOperand(2)); +} +  SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {   EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));   return DAG.getUNDEF(WidenVT); diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 81c51c49b72..5b00adb52a2 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -682,7 +682,7 @@ void TargetLowering::computeRegisterProperties() {        for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {          EVT SVT = (MVT::SimpleValueType)nVT;          if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && -            SVT.getVectorNumElements() > NElts) { +            SVT.getVectorNumElements() > NElts && NElts != 1) {            TransformToType[i] = SVT;            ValueTypeActions.setTypeAction(VT, Promote);            IsLegalWiderType = true; | 

