3 files changed, 10 insertions, 45 deletions

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index c44532e240f..66082df0108 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1617,29 +1617,14 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
   if (isa<FPMathOperator>(CI))
     MIB->copyIRFlags(CI);
 
-  for (auto &Arg : enumerate(CI.arg_operands())) {
+  for (auto &Arg : CI.arg_operands()) {
     // Some intrinsics take metadata parameters. Reject them.
-    if (isa<MetadataAsValue>(Arg.value()))
+    if (isa<MetadataAsValue>(Arg))
       return false;
-
-    // If this is required to be an immediate, don't materialize it in a
-    // register.
-    if (CI.paramHasAttr(Arg.index(), Attribute::ImmArg)) {
-      if (ConstantInt *CI = dyn_cast<ConstantInt>(Arg.value())) {
-        // imm arguments are more convenient than cimm (and realistically
-        // probably sufficient), so use them.
-        assert(CI->getBitWidth() <= 64 &&
-               "large intrinsic immediates not handled");
-        MIB.addImm(CI->getSExtValue());
-      } else {
-        MIB.addFPImm(cast<ConstantFP>(Arg.value()));
-      }
-    } else {
-      ArrayRef<Register> VRegs = getOrCreateVRegs(*Arg.value());
-      if (VRegs.size() > 1)
-        return false;
-      MIB.addUse(VRegs[0]);
-    }
+    ArrayRef<Register> VRegs = getOrCreateVRegs(*Arg);
+    if (VRegs.size() > 1)
+      return false;
+    MIB.addUse(VRegs[0]);
   }
 
   // Add a MachineMemOperand if it is a target mem intrinsic.
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 92420e697ce..af07f8f948f 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -373,13 +373,6 @@ LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
   return TRI->getSubRegIndexLaneMask(SubReg);
 }
 
-bool ScheduleDAGInstrs::deadDefHasNoUse(const MachineOperand &MO) {
-  auto RegUse = CurrentVRegUses.find(MO.getReg());
-  if (RegUse == CurrentVRegUses.end())
-    return true;
-  return (RegUse->LaneMask & getLaneMaskForMO(MO)).none();
-}
-
 /// Adds register output and data dependencies from this SUnit to instructions
 /// that occur later in the same scheduling region if they read from or write to
 /// the virtual register defined at OperIdx.
@@ -409,7 +402,8 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
   }
 
   if (MO.isDead()) {
-    assert(deadDefHasNoUse(MO) && "Dead defs should have no uses");
+    assert(CurrentVRegUses.find(Reg) == CurrentVRegUses.end() &&
+           "Dead defs should have no uses");
   } else {
     // Add data dependence to all uses we found so far.
     const TargetSubtargetInfo &ST = MF.getSubtarget();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 98f7d877c05..ce3255c081b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4768,22 +4768,8 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
 
   // Add all operands of the call to the operand list.
   for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
-    const Value *Arg = I.getArgOperand(i);
-    if (!I.paramHasAttr(i, Attribute::ImmArg)) {
-      Ops.push_back(getValue(Arg));
-      continue;
-    }
-
-    // Use TargetConstant instead of a regular constant for immarg.
-    EVT VT = TLI.getValueType(*DL, Arg->getType(), true);
-    if (const ConstantInt *CI = dyn_cast<ConstantInt>(Arg)) {
-      assert(CI->getBitWidth() <= 64 &&
-             "large intrinsic immediates not handled");
-      Ops.push_back(DAG.getTargetConstant(*CI, SDLoc(), VT));
-    } else {
-      Ops.push_back(
-          DAG.getTargetConstantFP(*cast<ConstantFP>(Arg), SDLoc(), VT));
-    }
+    SDValue Op = getValue(I.getArgOperand(i));
+    Ops.push_back(Op);
   }
 
   SmallVector<EVT, 4> ValueVTs;