diff options
Diffstat (limited to 'llvm/lib/CodeGen')
16 files changed, 1255 insertions, 1279 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp index 667870d4521..5dcf4ac92d4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp @@ -32,8 +32,8 @@ CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm, // HandleByVal - Allocate a stack slot large enough to pass an argument by // value. The size and alignment information of the argument is encoded in its // parameter attribute. -void CCState::HandleByVal(unsigned ValNo, MVT::ValueType ValVT, - MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo, +void CCState::HandleByVal(unsigned ValNo, MVT ValVT, + MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags) { unsigned Align = ArgFlags.getByValAlign(); @@ -62,12 +62,12 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) { unsigned NumArgs = TheArgs->getNumValues()-1; for (unsigned i = 0; i != NumArgs; ++i) { - MVT::ValueType ArgVT = TheArgs->getValueType(i); + MVT ArgVT = TheArgs->getValueType(i); ISD::ArgFlagsTy ArgFlags = cast<ARG_FLAGSSDNode>(TheArgs->getOperand(3+i))->getArgFlags(); if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { cerr << "Formal argument #" << i << " has unhandled type " - << MVT::getValueTypeString(ArgVT) << "\n"; + << ArgVT.getMVTString() << "\n"; abort(); } } @@ -78,12 +78,12 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) { void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) { // Determine which register each value should be copied into. for (unsigned i = 0, e = TheRet->getNumOperands() / 2; i != e; ++i) { - MVT::ValueType VT = TheRet->getOperand(i*2+1).getValueType(); + MVT VT = TheRet->getOperand(i*2+1).getValueType(); ISD::ArgFlagsTy ArgFlags = cast<ARG_FLAGSSDNode>(TheRet->getOperand(i*2+2))->getArgFlags(); if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){ cerr << "Return operand #" << i << " has unhandled type " - << MVT::getValueTypeString(VT) << "\n"; + << VT.getMVTString() << "\n"; abort(); } } @@ -95,12 +95,12 @@ void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) { void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) { unsigned NumOps = (TheCall->getNumOperands() - 5) / 2; for (unsigned i = 0; i != NumOps; ++i) { - MVT::ValueType ArgVT = TheCall->getOperand(5+2*i).getValueType(); + MVT ArgVT = TheCall->getOperand(5+2*i).getValueType(); ISD::ArgFlagsTy ArgFlags = cast<ARG_FLAGSSDNode>(TheCall->getOperand(5+2*i+1))->getArgFlags(); if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { cerr << "Call operand #" << i << " has unhandled type " - << MVT::getValueTypeString(ArgVT) << "\n"; + << ArgVT.getMVTString() << "\n"; abort(); } } @@ -110,10 +110,10 @@ void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) { /// incorporating info about the passed values into this state. void CCState::AnalyzeCallResult(SDNode *TheCall, CCAssignFn Fn) { for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) { - MVT::ValueType VT = TheCall->getValueType(i); + MVT VT = TheCall->getValueType(i); if (Fn(i, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { cerr << "Call result #" << i << " has unhandled type " - << MVT::getValueTypeString(VT) << "\n"; + << VT.getMVTString() << "\n"; abort(); } } diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 31cbdb9c787..d957bf93532 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -215,12 +215,12 @@ namespace { SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, SDOperand N3, ISD::CondCode CC, bool NotExtCompare = false); - SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, + SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, ISD::CondCode Cond, bool foldBooleans = true); SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); - SDOperand CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT); - SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); + SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT); + SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); SDOperand BuildSDIV(SDNode *N); SDOperand BuildUDIV(SDNode *N); SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); @@ -482,7 +482,7 @@ static bool isOneUseSetCC(SDOperand N) { } SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { @@ -887,7 +887,7 @@ SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { static SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); SDOperand N00 = N0.getOperand(0); SDOperand N01 = N0.getOperand(1); ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); @@ -904,7 +904,7 @@ SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { static SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, SelectionDAG &DAG) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); unsigned Opc = N->getOpcode(); bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); @@ -930,8 +930,8 @@ SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, cast<ConstantSDNode>(RHS)->isNullValue()) { std::swap(LHS, RHS); SDOperand Op0 = Slct.getOperand(0); - bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() - : Op0.getOperand(0).getValueType()); + bool isInt = (isSlctCC ? Op0.getValueType() : + Op0.getOperand(0).getValueType()).isInteger(); CC = ISD::getSetCCInverse(CC, isInt); DoXform = true; InvCC = true; @@ -956,10 +956,10 @@ SDOperand DAGCombiner::visitADD(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1001,14 +1001,14 @@ SDOperand DAGCombiner::visitADD(SDNode *N) { if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) return N1.getOperand(0); - if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) + if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); // fold (a+b) -> (a|b) iff a and b share no bits. - if (MVT::isInteger(VT) && !MVT::isVector(VT)) { + if (VT.isInteger() && !VT.isVector()) { APInt LHSZero, LHSOne; APInt RHSZero, RHSOne; - APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); if (LHSZero.getBoolValue()) { DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); @@ -1049,7 +1049,7 @@ SDOperand DAGCombiner::visitADDC(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // If the flag result is dead, turn this into an ADD. if (N->hasNUsesOfValue(0, 1)) @@ -1069,7 +1069,7 @@ SDOperand DAGCombiner::visitADDC(SDNode *N) { // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. APInt LHSZero, LHSOne; APInt RHSZero, RHSOne; - APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); if (LHSZero.getBoolValue()) { DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); @@ -1091,7 +1091,7 @@ SDOperand DAGCombiner::visitADDE(SDNode *N) { SDOperand CarryIn = N->getOperand(2); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - //MVT::ValueType VT = N0.getValueType(); + //MVT VT = N0.getValueType(); // canonicalize constant to RHS if (N0C && !N1C) { @@ -1115,10 +1115,10 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1158,10 +1158,10 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1242,10 +1242,10 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1261,7 +1261,7 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) { return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); // If we know the sign bits of both operands are zero, strength reduce to a // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); } @@ -1278,12 +1278,12 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) { unsigned lg2 = Log2_64(abs2); // Splat the sign bit into the register SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, - DAG.getConstant(MVT::getSizeInBits(VT)-1, + DAG.getConstant(VT.getSizeInBits()-1, TLI.getShiftAmountTy())); AddToWorkList(SGN.Val); // Add (N0 < 0) ? abs2 - 1 : 0; SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, - DAG.getConstant(MVT::getSizeInBits(VT)-lg2, + DAG.getConstant(VT.getSizeInBits()-lg2, TLI.getShiftAmountTy())); SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); AddToWorkList(SRL.Val); @@ -1320,10 +1320,10 @@ SDOperand DAGCombiner::visitUDIV(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1340,7 +1340,7 @@ SDOperand DAGCombiner::visitUDIV(SDNode *N) { if (N1.getOpcode() == ISD::SHL) { if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { if (SHC->getAPIntValue().isPowerOf2()) { - MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); + MVT ADDVT = N1.getOperand(1).getValueType(); SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), DAG.getConstant(SHC->getAPIntValue() .logBase2(), @@ -1371,14 +1371,14 @@ SDOperand DAGCombiner::visitSREM(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (srem c1, c2) -> c1%c2 if (N0C && N1C && !N1C->isNullValue()) return DAG.getNode(ISD::SREM, VT, N0, N1); // If we know the sign bits of both operands are zero, strength reduce to a // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) return DAG.getNode(ISD::UREM, VT, N0, N1); } @@ -1412,7 +1412,7 @@ SDOperand DAGCombiner::visitUREM(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (urem c1, c2) -> c1%c2 if (N0C && N1C && !N1C->isNullValue()) @@ -1427,7 +1427,7 @@ SDOperand DAGCombiner::visitUREM(SDNode *N) { if (SHC->getAPIntValue().isPowerOf2()) { SDOperand Add = DAG.getNode(ISD::ADD, VT, N1, - DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)), + DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); AddToWorkList(Add.Val); return DAG.getNode(ISD::AND, VT, N0, Add); @@ -1462,7 +1462,7 @@ SDOperand DAGCombiner::visitMULHS(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (mulhs x, 0) -> 0 if (N1C && N1C->isNullValue()) @@ -1470,7 +1470,7 @@ SDOperand DAGCombiner::visitMULHS(SDNode *N) { // fold (mulhs x, 1) -> (sra x, size(x)-1) if (N1C && N1C->getAPIntValue() == 1) return DAG.getNode(ISD::SRA, N0.getValueType(), N0, - DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, + DAG.getConstant(N0.getValueType().getSizeInBits()-1, TLI.getShiftAmountTy())); // fold (mulhs x, undef) -> 0 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) @@ -1483,7 +1483,7 @@ SDOperand DAGCombiner::visitMULHU(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (mulhu x, 0) -> 0 if (N1C && N1C->isNullValue()) @@ -1583,7 +1583,7 @@ SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { /// two operands of the same opcode, try to simplify it. SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); // For each of OP in AND/OR/XOR: @@ -1624,11 +1624,11 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { SDOperand LL, LR, RL, RR, CC0, CC1; ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N1.getValueType(); - unsigned BitWidth = MVT::getSizeInBits(VT); + MVT VT = N1.getValueType(); + unsigned BitWidth = VT.getSizeInBits(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1683,7 +1683,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && - MVT::isInteger(LL.getValueType())) { + LL.getValueType().isInteger()) { // fold (X == 0) & (Y == 0) -> (X|Y == 0) if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); @@ -1709,7 +1709,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { std::swap(RL, RR); } if (LL == RL && LR == RR) { - bool isInteger = MVT::isInteger(LL.getValueType()); + bool isInteger = LL.getValueType().isInteger(); ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); if (Result != ISD::SETCC_INVALID) return DAG.getSetCC(N0.getValueType(), LL, LR, Result); @@ -1724,18 +1724,18 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) // fold (and (sra)) -> (and (srl)) when possible. - if (!MVT::isVector(VT) && + if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); // fold (zext_inreg (extload x)) -> (zextload x) if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. unsigned BitWidth = N1.getValueSizeInBits(); if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, - BitWidth - MVT::getSizeInBits(EVT))) && + BitWidth - EVT.getSizeInBits())) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -1751,12 +1751,12 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. unsigned BitWidth = N1.getValueSizeInBits(); if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, - BitWidth - MVT::getSizeInBits(EVT))) && + BitWidth - EVT.getSizeInBits())) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -1775,7 +1775,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed() && N0.hasOneUse()) { - MVT::ValueType EVT, LoadedVT; + MVT EVT, LoadedVT; if (N1C->getAPIntValue() == 255) EVT = MVT::i8; else if (N1C->getAPIntValue() == 65535) @@ -1788,12 +1788,12 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { LoadedVT = LN0->getMemoryVT(); if (EVT != MVT::Other && LoadedVT > EVT && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { - MVT::ValueType PtrType = N0.getOperand(1).getValueType(); + MVT PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to add an offset to the pointer to // load the correct bytes. For little endian systems, we merely need to // read fewer bytes from the same pointer. - unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; - unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; + unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; + unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; unsigned Alignment = LN0->getAlignment(); SDOperand NewPtr = LN0->getBasePtr(); @@ -1823,10 +1823,10 @@ SDOperand DAGCombiner::visitOR(SDNode *N) { SDOperand LL, LR, RL, RR, CC0, CC1; ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N1.getValueType(); + MVT VT = N1.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1868,7 +1868,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) { ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && - MVT::isInteger(LL.getValueType())) { + LL.getValueType().isInteger()) { // fold (X != 0) | (Y != 0) -> (X|Y != 0) // fold (X < 0) | (Y < 0) -> (X|Y < 0) if (cast<ConstantSDNode>(LR)->isNullValue() && @@ -1892,7 +1892,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) { std::swap(RL, RR); } if (LL == RL && LR == RR) { - bool isInteger = MVT::isInteger(LL.getValueType()); + bool isInteger = LL.getValueType().isInteger(); ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); if (Result != ISD::SETCC_INVALID) return DAG.getSetCC(N0.getValueType(), LL, LR, Result); @@ -1959,7 +1959,7 @@ static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { // a rot[lr]. SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { // Must be a legal type. Expanded an promoted things won't work with rotates. - MVT::ValueType VT = LHS.getValueType(); + MVT VT = LHS.getValueType(); if (!TLI.isTypeLegal(VT)) return 0; // The target must have at least one rotate flavor. @@ -1991,7 +1991,7 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { std::swap(LHSMask , RHSMask ); } - unsigned OpSizeInBits = MVT::getSizeInBits(VT); + unsigned OpSizeInBits = VT.getSizeInBits(); SDOperand LHSShiftArg = LHSShift.getOperand(0); SDOperand LHSShiftAmt = LHSShift.getOperand(1); SDOperand RHSShiftAmt = RHSShift.getOperand(1); @@ -2115,10 +2115,10 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) { SDOperand LHS, RHS, CC; ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -2146,7 +2146,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) { return RXOR; // fold !(x cc y) -> (x !cc y) if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { - bool isInt = MVT::isInteger(LHS.getValueType()); + bool isInt = LHS.getValueType().isInteger(); ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), isInt); if (N0.getOpcode() == ISD::SETCC) @@ -2205,12 +2205,12 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) { } // fold (xor x, x) -> 0 if (N0 == N1) { - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { return DAG.getConstant(0, VT); } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { // Produce a vector of zeros. - SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); - std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); + SDOperand El = DAG.getConstant(0, VT.getVectorElementType()); + std::vector<SDOperand> Ops(VT.getVectorNumElements(), El); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } } @@ -2222,7 +2222,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) { } // Simplify the expression using non-local knowledge. - if (!MVT::isVector(VT) && + if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); @@ -2274,7 +2274,7 @@ SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) return SDOperand(); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // If this is a signed shift right, and the high bit is modified // by the logical operation, do not perform the transformation. @@ -2305,8 +2305,8 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N0.getValueType(); - unsigned OpSizeInBits = MVT::getSizeInBits(VT); + MVT VT = N0.getValueType(); + unsigned OpSizeInBits = VT.getSizeInBits(); // fold (shl c1, c2) -> c1<<c2 if (N0C && N1C) @@ -2322,7 +2322,7 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) { return N0; // if (shl x, c) is known to be zero, return 0 if (DAG.MaskedValueIsZero(SDOperand(N, 0), - APInt::getAllOnesValue(MVT::getSizeInBits(VT)))) + APInt::getAllOnesValue(VT.getSizeInBits()))) return DAG.getConstant(0, VT); if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); @@ -2364,7 +2364,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold (sra c1, c2) -> c1>>c2 if (N0C && N1C) @@ -2376,7 +2376,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) { if (N0C && N0C->isAllOnesValue()) return N0; // fold (sra x, c >= size(x)) -> undef - if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) + if (N1C && N1C->getValue() >= VT.getSizeInBits()) return DAG.getNode(ISD::UNDEF, VT); // fold (sra x, 0) -> x if (N1C && N1C->isNullValue()) @@ -2384,8 +2384,8 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) { // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports // sext_inreg. if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { - unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); - MVT::ValueType EVT; + unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue(); + MVT EVT; switch (LowBits) { default: EVT = MVT::Other; break; case 1: EVT = MVT::i1; break; @@ -2402,7 +2402,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) { if (N1C && N0.getOpcode() == ISD::SRA) { if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { unsigned Sum = N1C->getValue() + C1->getValue(); - if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; + if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), DAG.getConstant(Sum, N1C->getValueType(0))); } @@ -2418,8 +2418,9 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) { const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); if (N01C && N1C) { // Determine what the truncate's result bitsize and type would be. - unsigned VTValSize = MVT::getSizeInBits(VT); - MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue()); + unsigned VTValSize = VT.getSizeInBits(); + MVT TruncVT = + MVT::getIntegerVT(VTValSize - N1C->getValue()); // Determine the residual right-shift amount. unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); @@ -2458,8 +2459,8 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT::ValueType VT = N0.getValueType(); - unsigned OpSizeInBits = MVT::getSizeInBits(VT); + MVT VT = N0.getValueType(); + unsigned OpSizeInBits = VT.getSizeInBits(); // fold (srl c1, c2) -> c1 >>u c2 if (N0C && N1C) @@ -2492,8 +2493,8 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) { // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { // Shifting in all undef bits? - MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); - if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) + MVT SmallVT = N0.getOperand(0).getValueType(); + if (N1C->getValue() >= SmallVT.getSizeInBits()) return DAG.getNode(ISD::UNDEF, VT); SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); @@ -2503,16 +2504,16 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) { // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign // bit, which is unmodified by sra. - if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { + if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) { if (N0.getOpcode() == ISD::SRA) return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); } // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). if (N1C && N0.getOpcode() == ISD::CTLZ && - N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) { + N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { APInt KnownZero, KnownOne; - APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); // If any of the input bits are KnownOne, then the input couldn't be all @@ -2551,7 +2552,7 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) { SDOperand DAGCombiner::visitCTLZ(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (ctlz c1) -> c2 if (isa<ConstantSDNode>(N0)) @@ -2561,7 +2562,7 @@ SDOperand DAGCombiner::visitCTLZ(SDNode *N) { SDOperand DAGCombiner::visitCTTZ(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (cttz c1) -> c2 if (isa<ConstantSDNode>(N0)) @@ -2571,7 +2572,7 @@ SDOperand DAGCombiner::visitCTTZ(SDNode *N) { SDOperand DAGCombiner::visitCTPOP(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (ctpop c1) -> c2 if (isa<ConstantSDNode>(N0)) @@ -2586,8 +2587,8 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) { ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType VT0 = N0.getValueType(); + MVT VT = N->getValueType(0); + MVT VT0 = N0.getValueType(); // fold select C, X, X -> X if (N1 == N2) @@ -2599,16 +2600,16 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) { if (N0C && N0C->isNullValue()) return N2; // fold select C, 1, X -> C | X - if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1) + if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) return DAG.getNode(ISD::OR, VT, N0, N2); // fold select C, 0, 1 -> ~C - if (MVT::isInteger(VT) && MVT::isInteger(VT0) && + if (VT.isInteger() && VT0.isInteger() && N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); if (VT == VT0) return XORNode; AddToWorkList(XORNode.Val); - if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) + if (VT.getSizeInBits() > VT0.getSizeInBits()) return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); return DAG.getNode(ISD::TRUNCATE, VT, XORNode); } @@ -2626,13 +2627,13 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) { } // fold select C, X, 0 -> C & X // FIXME: this should check for C type == X type, not i1? - if (MVT::i1 == VT && N2C && N2C->isNullValue()) + if (VT == MVT::i1 && N2C && N2C->isNullValue()) return DAG.getNode(ISD::AND, VT, N0, N1); // fold X ? X : Y --> X ? 1 : Y --> X | Y - if (MVT::i1 == VT && N0 == N1) + if (VT == MVT::i1 && N0 == N1) return DAG.getNode(ISD::OR, VT, N0, N2); // fold X ? Y : X --> X ? Y : 0 --> X & Y - if (MVT::i1 == VT && N0 == N2) + if (VT == MVT::i1 && N0 == N2) return DAG.getNode(ISD::AND, VT, N0, N1); // If we can fold this based on the true/false value, do so. @@ -2766,7 +2767,7 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (sext c1) -> c1 if (isa<ConstantSDNode>(N0)) @@ -2790,9 +2791,9 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { // See if the value being truncated is already sign extended. If so, just // eliminate the trunc/sext pair. SDOperand Op = N0.getOperand(0); - unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); - unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); - unsigned DestBits = MVT::getSizeInBits(VT); + unsigned OpBits = Op.getValueType().getSizeInBits(); + unsigned MidBits = N0.getValueType().getSizeInBits(); + unsigned DestBits = VT.getSizeInBits(); unsigned NumSignBits = DAG.ComputeNumSignBits(Op); if (OpBits == DestBits) { @@ -2866,7 +2867,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -2899,7 +2900,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (zext c1) -> c1 if (isa<ConstantSDNode>(N0)) @@ -2943,7 +2944,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { X = DAG.getNode(ISD::TRUNCATE, VT, X); } APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); - Mask.zext(MVT::getSizeInBits(VT)); + Mask.zext(VT.getSizeInBits()); return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); } @@ -2989,7 +2990,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, @@ -3015,7 +3016,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (aext c1) -> c1 if (isa<ConstantSDNode>(N0)) @@ -3060,7 +3061,7 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { X = DAG.getNode(ISD::TRUNCATE, VT, X); } APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); - Mask.zext(MVT::getSizeInBits(VT)); + Mask.zext(VT.getSizeInBits()); return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); } @@ -3087,7 +3088,7 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -3154,8 +3155,8 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { unsigned Opc = N->getOpcode(); ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType EVT = N->getValueType(0); + MVT VT = N->getValueType(0); + MVT EVT = N->getValueType(0); // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then // extended to VT. @@ -3166,7 +3167,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { return SDOperand(); } - unsigned EVTBits = MVT::getSizeInBits(EVT); + unsigned EVTBits = EVT.getSizeInBits(); unsigned ShAmt = 0; bool CombineSRL = false; if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { @@ -3175,7 +3176,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { // Is the shift amount a multiple of size of VT? if ((ShAmt & (EVTBits-1)) == 0) { N0 = N0.getOperand(0); - if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) + if (N0.getValueType().getSizeInBits() <= EVTBits) return SDOperand(); CombineSRL = true; } @@ -3188,15 +3189,15 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { // that it is already zero extended. // FIXME: This should be reevaluated. VT != MVT::i1) { - assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && + assert(N0.getValueType().getSizeInBits() > EVTBits && "Cannot truncate to larger type!"); LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT::ValueType PtrType = N0.getOperand(1).getValueType(); + MVT PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to adjust the offset to the pointer to // load the correct bytes. if (TLI.isBigEndian()) { - unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); - unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); + unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits(); + unsigned EVTStoreBits = EVT.getStoreSizeInBits(); ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; } uint64_t PtrOff = ShAmt / 8; @@ -3235,17 +3236,17 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); - unsigned VTBits = MVT::getSizeInBits(VT); - unsigned EVTBits = MVT::getSizeInBits(EVT); + MVT VT = N->getValueType(0); + MVT EVT = cast<VTSDNode>(N1)->getVT(); + unsigned VTBits = VT.getSizeInBits(); + unsigned EVTBits = EVT.getSizeInBits(); // fold (sext_in_reg c1) -> c1 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); // If the input is already sign extended, just drop the extension. - if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) + if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) return N0; // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 @@ -3274,11 +3275,11 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. if (N0.getOpcode() == ISD::SRL) { if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) - if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { + if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) { // We can turn this into an SRA iff the input to the SRL is already sign // extended enough. unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); - if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) + if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits) return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); } } @@ -3318,7 +3319,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // noop truncate if (N0.getValueType() == N->getValueType(0)) @@ -3349,7 +3350,7 @@ SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { // -> trunc y SDOperand Shorter = GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), - MVT::getSizeInBits(VT))); + VT.getSizeInBits())); if (Shorter.Val) return DAG.getNode(ISD::TRUNCATE, VT, Shorter); @@ -3367,22 +3368,22 @@ static SDNode *getBuildPairElt(SDNode *N, unsigned i) { /// CombineConsecutiveLoads - build_pair (load, load) -> load /// if load locations are consecutive. -SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT) { +SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { assert(N->getOpcode() == ISD::BUILD_PAIR); SDNode *LD1 = getBuildPairElt(N, 0); if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) return SDOperand(); - MVT::ValueType LD1VT = LD1->getValueType(0); + MVT LD1VT = LD1->getValueType(0); SDNode *LD2 = getBuildPairElt(N, 1); const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); if (ISD::isNON_EXTLoad(LD2) && LD2->hasOneUse() && - TLI.isConsecutiveLoad(LD2, LD1, MVT::getSizeInBits(LD1VT)/8, 1, MFI)) { + TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { LoadSDNode *LD = cast<LoadSDNode>(LD1); unsigned Align = LD->getAlignment(); unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(VT)); + getABITypeAlignment(VT.getTypeForMVT()); if ((!AfterLegalize || TLI.isTypeLegal(VT)) && TLI.isOperationLegal(ISD::LOAD, VT) && NewAlign <= Align) return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), @@ -3394,7 +3395,7 @@ SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT) { SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // If the input is a BUILD_VECTOR with all constant elements, fold this now. // Only do this before legalize, since afterward the target may be depending @@ -3402,7 +3403,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { // First check to see if this is all constant. if (!AfterLegalize && N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && - MVT::isVector(VT)) { + VT.isVector()) { bool isSimple = true; for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) if (N0.getOperand(i).getOpcode() != ISD::UNDEF && @@ -3412,8 +3413,8 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { break; } - MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); - assert(!MVT::isVector(DestEltVT) && + MVT DestEltVT = N->getValueType(0).getVectorElementType(); + assert(!DestEltVT.isVector() && "Element type of vector ValueType must not be vector!"); if (isSimple) { return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); @@ -3435,7 +3436,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { TLI.isOperationLegal(ISD::LOAD, VT)) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); unsigned Align = TLI.getTargetMachine().getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(VT)); + getABITypeAlignment(VT.getTypeForMVT()); unsigned OrigAlign = LN0->getAlignment(); if (Align <= OrigAlign) { SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), @@ -3452,11 +3453,11 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) // This often reduces constant pool loads. if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && - N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { + N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) { SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); AddToWorkList(NewConv.Val); - APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); + APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); if (N0.getOpcode() == ISD::FNEG) return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); assert(N0.getOpcode() == ISD::FABS); @@ -3468,14 +3469,15 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { // to an fneg or fabs. if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(0)) && - MVT::isInteger(VT) && !MVT::isVector(VT)) { - unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); - SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), + VT.isInteger() && !VT.isVector()) { + unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); + SDOperand X = DAG.getNode(ISD::BIT_CONVERT, + MVT::getIntegerVT(OrigXWidth), N0.getOperand(1)); AddToWorkList(X.Val); // If X has a different width than the result/lhs, sext it or truncate it. - unsigned VTWidth = MVT::getSizeInBits(VT); + unsigned VTWidth = VT.getSizeInBits(); if (OrigXWidth < VTWidth) { X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); AddToWorkList(X.Val); @@ -3489,7 +3491,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { AddToWorkList(X.Val); } - APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); + APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); AddToWorkList(X.Val); @@ -3511,7 +3513,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { } SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); return CombineConsecutiveLoads(N, VT); } @@ -3519,14 +3521,14 @@ SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) { /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the /// destination element value type. SDOperand DAGCombiner:: -ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { - MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); +ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { + MVT SrcEltVT = BV->getOperand(0).getValueType(); // If this is already the right type, we're done. if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); - unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); - unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); + unsigned SrcBitSize = SrcEltVT.getSizeInBits(); + unsigned DstBitSize = DstEltVT.getSizeInBits(); // If this is a conversion of N elements of one type to N elements of another // type, convert each element. This handles FP<->INT cases. @@ -3536,29 +3538,28 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); AddToWorkList(Ops.back().Val); } - MVT::ValueType VT = - MVT::getVectorType(DstEltVT, - MVT::getVectorNumElements(BV->getValueType(0))); + MVT VT = MVT::getVectorVT(DstEltVT, + BV->getValueType(0).getVectorNumElements()); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } // Otherwise, we're growing or shrinking the elements. To avoid having to // handle annoying details of growing/shrinking FP values, we convert them to // int first. - if (MVT::isFloatingPoint(SrcEltVT)) { + if (SrcEltVT.isFloatingPoint()) { // Convert the input float vector to a int vector where the elements are the // same sizes. assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); - MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; + MVT IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; SrcEltVT = IntVT; } // Now we know the input is an integer vector. If the output is a FP type, // convert to integer first, then to FP of the right size. - if (MVT::isFloatingPoint(DstEltVT)) { + if (DstEltVT.isFloatingPoint()) { assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); - MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; + MVT TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; // Next, convert to FP elements of the same size. @@ -3567,7 +3568,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { // Okay, we know the src/dst types are both integers of differing types. // Handling growing first. - assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); + assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); if (SrcBitSize < DstBitSize) { unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; @@ -3594,7 +3595,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); } - MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); + MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } @@ -3602,8 +3603,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { // turns into multiple outputs. bool isS2V = ISD::isScalarToVector(BV); unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; - MVT::ValueType VT = MVT::getVectorType(DstEltVT, - NumOutputsPerInput * BV->getNumOperands()); + MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); SmallVector<SDOperand, 8> Ops; for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { @@ -3635,10 +3635,10 @@ SDOperand DAGCombiner::visitFADD(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -3672,10 +3672,10 @@ SDOperand DAGCombiner::visitFSUB(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -3702,10 +3702,10 @@ SDOperand DAGCombiner::visitFMUL(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -3749,10 +3749,10 @@ SDOperand DAGCombiner::visitFDIV(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -3782,7 +3782,7 @@ SDOperand DAGCombiner::visitFREM(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (frem c1, c2) -> fmod(c1,c2) if (N0CFP && N1CFP && VT != MVT::ppcf128) @@ -3796,7 +3796,7 @@ SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); @@ -3839,7 +3839,7 @@ SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (sint_to_fp c1) -> c1fp if (N0C && N0.getValueType() != MVT::ppcf128) @@ -3850,7 +3850,7 @@ SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (uint_to_fp c1) -> c1fp if (N0C && N0.getValueType() != MVT::ppcf128) @@ -3861,7 +3861,7 @@ SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (fp_to_sint c1fp) -> c1 if (N0CFP) @@ -3872,7 +3872,7 @@ SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (fp_to_uint c1fp) -> c1 if (N0CFP && VT != MVT::ppcf128) @@ -3884,7 +3884,7 @@ SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (fp_round c1fp) -> c1fp if (N0CFP && N0.getValueType() != MVT::ppcf128) @@ -3915,8 +3915,8 @@ SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + MVT VT = N->getValueType(0); + MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); // fold (fp_round_inreg c1fp) -> c1fp @@ -3930,7 +3930,7 @@ SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. if (N->hasOneUse() && @@ -3981,13 +3981,13 @@ SDOperand DAGCombiner::visitFNEG(SDNode *N) { // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading // constant pool values. if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && - MVT::isInteger(N0.getOperand(0).getValueType()) && - !MVT::isVector(N0.getOperand(0).getValueType())) { + N0.getOperand(0).getValueType().isInteger() && + !N0.getOperand(0).getValueType().isVector()) { SDOperand Int = N0.getOperand(0); - MVT::ValueType IntVT = Int.getValueType(); - if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { + MVT IntVT = Int.getValueType(); + if (IntVT.isInteger() && !IntVT.isVector()) { Int = DAG.getNode(ISD::XOR, IntVT, Int, - DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); + DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); AddToWorkList(Int.Val); return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); } @@ -3999,7 +3999,7 @@ SDOperand DAGCombiner::visitFNEG(SDNode *N) { SDOperand DAGCombiner::visitFABS(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (fabs c1) -> fabs(c1) if (N0CFP && VT != MVT::ppcf128) @@ -4015,13 +4015,13 @@ SDOperand DAGCombiner::visitFABS(SDNode *N) { // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading // constant pool values. if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && - MVT::isInteger(N0.getOperand(0).getValueType()) && - !MVT::isVector(N0.getOperand(0).getValueType())) { + N0.getOperand(0).getValueType().isInteger() && + !N0.getOperand(0).getValueType().isVector()) { SDOperand Int = N0.getOperand(0); - MVT::ValueType IntVT = Int.getValueType(); - if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { + MVT IntVT = Int.getValueType(); + if (IntVT.isInteger() && !IntVT.isVector()) { Int = DAG.getNode(ISD::AND, IntVT, Int, - DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); + DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); AddToWorkList(Int.Val); return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); } @@ -4093,7 +4093,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { bool isLoad = true; SDOperand Ptr; - MVT::ValueType VT; + MVT VT; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { if (LD->isIndexed()) return false; @@ -4214,7 +4214,7 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { bool isLoad = true; SDOperand Ptr; - MVT::ValueType VT; + MVT VT; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { if (LD->isIndexed()) return false; @@ -4513,9 +4513,9 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) { if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && ST->isUnindexed()) { unsigned Align = ST->getAlignment(); - MVT::ValueType SVT = Value.getOperand(0).getValueType(); + MVT SVT = Value.getOperand(0).getValueType(); unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(SVT)); + getABITypeAlignment(SVT.getTypeForMVT()); if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), Align); @@ -4525,7 +4525,7 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) { if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { if (Value.getOpcode() != ISD::TargetConstantFP) { SDOperand Tmp; - switch (CFP->getValueType(0)) { + switch (CFP->getValueType(0).getSimpleVT()) { default: assert(0 && "Unknown FP type"); case MVT::f80: // We don't do this for these yet. case MVT::f128: @@ -4610,14 +4610,14 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) { // FIXME: is there such a thing as a truncating indexed store? if (ST->isTruncatingStore() && ST->isUnindexed() && - MVT::isInteger(Value.getValueType())) { + Value.getValueType().isInteger()) { // See if we can simplify the input to this truncstore with knowledge that // only the low bits are being used. For example: // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" SDOperand Shorter = GetDemandedBits(Value, APInt::getLowBitsSet(Value.getValueSizeInBits(), - MVT::getSizeInBits(ST->getMemoryVT()))); + ST->getMemoryVT().getSizeInBits())); AddToWorkList(Value.Val); if (Shorter.Val) return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), @@ -4629,7 +4629,7 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) { if (SimplifyDemandedBits(Value, APInt::getLowBitsSet( Value.getValueSizeInBits(), - MVT::getSizeInBits(ST->getMemoryVT())))) + ST->getMemoryVT().getSizeInBits()))) return SDOperand(N, 0); } @@ -4695,17 +4695,17 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { if (isa<ConstantSDNode>(EltNo)) { unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); bool NewLoad = false; - MVT::ValueType VT = InVec.getValueType(); - MVT::ValueType EVT = MVT::getVectorElementType(VT); - MVT::ValueType LVT = EVT; + MVT VT = InVec.getValueType(); + MVT EVT = VT.getVectorElementType(); + MVT LVT = EVT; if (InVec.getOpcode() == ISD::BIT_CONVERT) { - MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); - if (!MVT::isVector(BCVT) - || (MVT::getSizeInBits(EVT) > - MVT::getSizeInBits(MVT::getVectorElementType(BCVT)))) + MVT BCVT = InVec.getOperand(0).getValueType(); + if (!BCVT.isVector() + || (EVT.getSizeInBits() > + BCVT.getVectorElementType().getSizeInBits())) return SDOperand(); InVec = InVec.getOperand(0); - EVT = MVT::getVectorElementType(BCVT); + EVT = BCVT.getVectorElementType(); NewLoad = true; } @@ -4739,7 +4739,7 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { // Check the resultant load doesn't need a higher alignment than the // original load. unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(LVT)); + getABITypeAlignment(LVT.getTypeForMVT()); if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) return SDOperand(); Align = NewAlign; @@ -4747,10 +4747,10 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { SDOperand NewPtr = LN0->getBasePtr(); if (Elt) { - unsigned PtrOff = MVT::getSizeInBits(LVT) * Elt / 8; - MVT::ValueType PtrType = NewPtr.getValueType(); + unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; + MVT PtrType = NewPtr.getValueType(); if (TLI.isBigEndian()) - PtrOff = MVT::getSizeInBits(VT) / 8 - PtrOff; + PtrOff = VT.getSizeInBits() / 8 - PtrOff; NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, DAG.getConstant(PtrOff, PtrType)); } @@ -4764,9 +4764,9 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { unsigned NumInScalars = N->getNumOperands(); - MVT::ValueType VT = N->getValueType(0); - unsigned NumElts = MVT::getVectorNumElements(VT); - MVT::ValueType EltType = MVT::getVectorElementType(VT); + MVT VT = N->getValueType(0); + unsigned NumElts = VT.getVectorNumElements(); + MVT EltType = VT.getVectorElementType(); // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from @@ -4830,7 +4830,7 @@ SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { } // Add count and size info. - MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); + MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); // Return the new VECTOR_SHUFFLE node. SDOperand Ops[5]; @@ -4933,7 +4933,7 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { // look though conversions that change things like v4f32 to v2f64. if (V->getOpcode() == ISD::BIT_CONVERT) { SDOperand ConvInput = V->getOperand(0); - if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) + if (ConvInput.getValueType().getVectorNumElements() == NumElts) V = ConvInput.Val; } @@ -5006,7 +5006,7 @@ SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { std::vector<SDOperand> IdxOps; unsigned NumOps = RHS.getNumOperands(); unsigned NumElts = NumOps; - MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); + MVT EVT = RHS.getValueType().getVectorElementType(); for (unsigned i = 0; i != NumElts; ++i) { SDOperand Elt = RHS.getOperand(i); if (!isa<ConstantSDNode>(Elt)) @@ -5024,7 +5024,7 @@ SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { return SDOperand(); // Return the new VECTOR_SHUFFLE node. - MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); + MVT VT = MVT::getVectorVT(EVT, NumElts); std::vector<SDOperand> Ops; LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); Ops.push_back(LHS); @@ -5052,10 +5052,10 @@ SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { // things. Simplifying them may result in a loss of legality. if (AfterLegalize) return SDOperand(); - MVT::ValueType VT = N->getValueType(0); - assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); + MVT VT = N->getValueType(0); + assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); - MVT::ValueType EltType = MVT::getVectorElementType(VT); + MVT EltType = VT.getVectorElementType(); SDOperand LHS = N->getOperand(0); SDOperand RHS = N->getOperand(1); SDOperand Shuffle = XformToShuffleWithZero(N); @@ -5095,7 +5095,7 @@ SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { } if (Ops.size() == LHS.getNumOperands()) { - MVT::ValueType VT = LHS.getValueType(); + MVT VT = LHS.getValueType(); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } } @@ -5217,7 +5217,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, SDOperand N3, ISD::CondCode CC, bool NotExtCompare) { - MVT::ValueType VT = N2.getValueType(); + MVT VT = N2.getValueType(); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); @@ -5255,18 +5255,18 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, // Check to see if we can perform the "gzip trick", transforming // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && - MVT::isInteger(N0.getValueType()) && - MVT::isInteger(N2.getValueType()) && + N0.getValueType().isInteger() && + N2.getValueType().isInteger() && (N1C->isNullValue() || // (a < 0) ? b : 0 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 - MVT::ValueType XType = N0.getValueType(); - MVT::ValueType AType = N2.getValueType(); + MVT XType = N0.getValueType(); + MVT AType = N2.getValueType(); if (XType >= AType) { // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a // single-bit constant. if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { unsigned ShCtV = N2C->getAPIntValue().logBase2(); - ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; + ShCtV = XType.getSizeInBits()-ShCtV-1; SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); AddToWorkList(Shift.Val); @@ -5277,7 +5277,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, return DAG.getNode(ISD::AND, AType, Shift, N2); } SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); AddToWorkList(Shift.Val); if (XType > AType) { @@ -5327,7 +5327,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, // FIXME: Turn all of these into setcc if setcc if setcc is legal // otherwise, go ahead with the folds. if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { - MVT::ValueType XType = N0.getValueType(); + MVT XType = N0.getValueType(); if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); if (Res.getValueType() != VT) @@ -5340,7 +5340,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, TLI.isOperationLegal(ISD::CTLZ, XType)) { SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); return DAG.getNode(ISD::SRL, XType, Ctlz, - DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), + DAG.getConstant(Log2_32(XType.getSizeInBits()), TLI.getShiftAmountTy())); } // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) @@ -5351,13 +5351,13 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, DAG.getConstant(~0ULL, XType)); return DAG.getNode(ISD::SRL, XType, DAG.getNode(ISD::AND, XType, NegN0, NotN0), - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); } // setgt X, -1 -> xor (srl (X, size(X)-1), 1) if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); } @@ -5367,10 +5367,10 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, // Y = sra (X, size(X)-1); xor (add (X, Y), Y) if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && - N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { - MVT::ValueType XType = N0.getValueType(); + N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { + MVT XType = N0.getValueType(); SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); AddToWorkList(Shift.Val); @@ -5382,10 +5382,10 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { - MVT::ValueType XType = N0.getValueType(); - if (SubC->isNullValue() && MVT::isInteger(XType)) { + MVT XType = N0.getValueType(); + if (SubC->isNullValue() && XType.isInteger()) { SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); AddToWorkList(Shift.Val); @@ -5399,7 +5399,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, } /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. -SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, +SDOperand DAGCombiner::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, ISD::CondCode Cond, bool foldBooleans) { TargetLowering::DAGCombinerInfo @@ -5502,13 +5502,13 @@ bool DAGCombiner::FindAliasInfo(SDNode *N, const Value *&SrcValue, int &SrcValueOffset) { if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { Ptr = LD->getBasePtr(); - Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; + Size = LD->getMemoryVT().getSizeInBits() >> 3; SrcValue = LD->getSrcValue(); SrcValueOffset = LD->getSrcValueOffset(); return true; } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { Ptr = ST->getBasePtr(); - Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; + Size = ST->getMemoryVT().getSizeInBits() >> 3; SrcValue = ST->getSrcValue(); SrcValueOffset = ST->getSrcValueOffset(); } else { diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 99f1a0355d5..83ba08da18f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -128,13 +128,13 @@ public: /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of /// smaller integer type, or we need to promote it to a larger type. - LegalizeAction getTypeAction(MVT::ValueType VT) const { + LegalizeAction getTypeAction(MVT VT) const { return (LegalizeAction)ValueTypeActions.getTypeAction(VT); } /// isTypeLegal - Return true if this type is legal on this target. /// - bool isTypeLegal(MVT::ValueType VT) const { + bool isTypeLegal(MVT VT) const { return getTypeAction(VT) == Legal; } @@ -196,7 +196,7 @@ private: /// /// If this is a legal shuffle, this method returns the (possibly promoted) /// build_vector Mask. If it's not a legal shuffle, it returns null. - SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; + SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const; bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, SmallPtrSet<SDNode*, 32> &NodesLeadingTo); @@ -205,20 +205,14 @@ private: SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, SDOperand &Hi); - SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, - SDOperand Source); + SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source); - SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, - MVT::ValueType DestVT); + SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT); SDOperand ExpandBUILD_VECTOR(SDNode *Node); SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); - SDOperand ExpandLegalINT_TO_FP(bool isSigned, - SDOperand LegalOp, - MVT::ValueType DestVT); - SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, - bool isSigned); - SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, - bool isSigned); + SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT); + SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned); + SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned); SDOperand ExpandBSWAP(SDOperand Op); SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); @@ -238,8 +232,7 @@ private: /// /// Note that this will also return true for shuffles that are promoted to a /// different type. -SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, - SDOperand Mask) const { +SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const { switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { default: return 0; case TargetLowering::Legal: @@ -248,11 +241,11 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, case TargetLowering::Promote: { // If this is promoted to a different type, convert the shuffle mask and // ask if it is legal in the promoted type! - MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); + MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); // If we changed # elements, change the shuffle mask. unsigned NumEltsGrowth = - MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); + NVT.getVectorNumElements() / VT.getVectorNumElements(); assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); if (NumEltsGrowth > 1) { // Renumber the elements. @@ -458,20 +451,20 @@ bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, /// HandleOp - Legalize, Promote, or Expand the specified operand as /// appropriate for its type. void SelectionDAGLegalize::HandleOp(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); switch (getTypeAction(VT)) { default: assert(0 && "Bad type action!"); case Legal: (void)LegalizeOp(Op); break; case Promote: (void)PromoteOp(Op); break; case Expand: - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { // If this is an illegal scalar, expand it into its two component // pieces. SDOperand X, Y; if (Op.getOpcode() == ISD::TargetConstant) break; // Allow illegal target nodes. ExpandOp(Op, X, Y); - } else if (MVT::getVectorNumElements(VT) == 1) { + } else if (VT.getVectorNumElements() == 1) { // If this is an illegal single element vector, convert it to a // scalar operation. (void)ScalarizeVectorOp(Op); @@ -497,7 +490,7 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, // double. This shrinks FP constants and canonicalizes them for targets where // an FP extending load is the same cost as a normal load (such as on the x87 // fp stack or PPC FP unit). - MVT::ValueType VT = CFP->getValueType(0); + MVT VT = CFP->getValueType(0); ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); if (!UseCP) { if (VT!=MVT::f64 && VT!=MVT::f32) @@ -506,16 +499,16 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, (VT == MVT::f64) ? MVT::i64 : MVT::i32); } - MVT::ValueType OrigVT = VT; - MVT::ValueType SVT = VT; + MVT OrigVT = VT; + MVT SVT = VT; while (SVT != MVT::f32) { - SVT = (unsigned)SVT - 1; + SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && // Only do this if the target has a native EXTLOAD instruction from // smaller type. TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && TLI.ShouldShrinkFPConstant(OrigVT)) { - const Type *SType = MVT::getTypeForValueType(SVT); + const Type *SType = SVT.getTypeForMVT(); LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); VT = SVT; Extend = true; @@ -535,13 +528,13 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise /// operations. static -SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, +SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, SelectionDAG &DAG, TargetLowering &TLI) { - MVT::ValueType VT = Node->getValueType(0); - MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); + MVT VT = Node->getValueType(0); + MVT SrcVT = Node->getOperand(1).getValueType(); assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && "fcopysign expansion only supported for f32 and f64"); - MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; + MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; // First get the sign bit of second operand. SDOperand Mask1 = (SrcVT == MVT::f64) @@ -551,7 +544,7 @@ SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); // Shift right or sign-extend it if the two operands have different types. - int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); + int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); if (SizeDiff > 0) { SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); @@ -579,17 +572,17 @@ SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, SDOperand Chain = ST->getChain(); SDOperand Ptr = ST->getBasePtr(); SDOperand Val = ST->getValue(); - MVT::ValueType VT = Val.getValueType(); + MVT VT = Val.getValueType(); int Alignment = ST->getAlignment(); int SVOffset = ST->getSrcValueOffset(); - if (MVT::isFloatingPoint(ST->getMemoryVT()) || - MVT::isVector(ST->getMemoryVT())) { + if (ST->getMemoryVT().isFloatingPoint() || + ST->getMemoryVT().isVector()) { // Expand to a bitconvert of the value to the integer type of the // same size, then a (misaligned) int store. - MVT::ValueType intVT; - if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128) + MVT intVT; + if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) intVT = MVT::i128; - else if (MVT::is64BitVector(VT) || VT==MVT::f64) + else if (VT.is64BitVector() || VT==MVT::f64) intVT = MVT::i64; else if (VT==MVT::f32) intVT = MVT::i32; @@ -600,12 +593,13 @@ SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), SVOffset, ST->isVolatile(), Alignment); } - assert(MVT::isInteger(ST->getMemoryVT()) && - !MVT::isVector(ST->getMemoryVT()) && + assert(ST->getMemoryVT().isInteger() && + !ST->getMemoryVT().isVector() && "Unaligned store of unknown type."); // Get the half-size VT - MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1; - int NumBits = MVT::getSizeInBits(NewStoredVT); + MVT NewStoredVT = + (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); + int NumBits = NewStoredVT.getSizeInBits(); int IncrementSize = NumBits / 8; // Divide the stored value in two parts. @@ -635,16 +629,16 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, int SVOffset = LD->getSrcValueOffset(); SDOperand Chain = LD->getChain(); SDOperand Ptr = LD->getBasePtr(); - MVT::ValueType VT = LD->getValueType(0); - MVT::ValueType LoadedVT = LD->getMemoryVT(); - if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) { + MVT VT = LD->getValueType(0); + MVT LoadedVT = LD->getMemoryVT(); + if (VT.isFloatingPoint() || VT.isVector()) { // Expand to a (misaligned) integer load of the same size, // then bitconvert to floating point or vector. - MVT::ValueType intVT; - if (MVT::is128BitVector(LoadedVT) || + MVT intVT; + if (LoadedVT.is128BitVector() || LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) intVT = MVT::i128; - else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64) + else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) intVT = MVT::i64; else if (LoadedVT == MVT::f32) intVT = MVT::i32; @@ -655,21 +649,21 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, SVOffset, LD->isVolatile(), LD->getAlignment()); SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); - if (MVT::isFloatingPoint(VT) && LoadedVT != VT) + if (VT.isFloatingPoint() && LoadedVT != VT) Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); SDOperand Ops[] = { Result, Chain }; return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); } - assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) && + assert(LoadedVT.isInteger() && !LoadedVT.isVector() && "Unaligned load of unsupported type."); // Compute the new VT that is half the size of the old one. This is an // integer MVT. - unsigned NumBits = MVT::getSizeInBits(LoadedVT); - MVT::ValueType NewLoadedVT; - NewLoadedVT = MVT::getIntegerType(NumBits/2); + unsigned NumBits = LoadedVT.getSizeInBits(); + MVT NewLoadedVT; + NewLoadedVT = MVT::getIntegerVT(NumBits/2); NumBits >>= 1; unsigned Alignment = LD->getAlignment(); @@ -717,23 +711,23 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, /// no way of lowering. "Unroll" the vector, splitting out the scalars and /// operating on each element individually. SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); assert(isTypeLegal(VT) && "Caller should expand or promote operands that are not legal!"); assert(Op.Val->getNumValues() == 1 && "Can't unroll a vector with multiple results!"); - unsigned NE = MVT::getVectorNumElements(VT); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); + unsigned NE = VT.getVectorNumElements(); + MVT EltVT = VT.getVectorElementType(); SmallVector<SDOperand, 8> Scalars; SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); for (unsigned i = 0; i != NE; ++i) { for (unsigned j = 0; j != Op.getNumOperands(); ++j) { SDOperand Operand = Op.getOperand(j); - MVT::ValueType OperandVT = Operand.getValueType(); - if (MVT::isVector(OperandVT)) { + MVT OperandVT = Operand.getValueType(); + if (OperandVT.isVector()) { // A vector operand; extract a single element. - MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); + MVT OperandEltVT = OperandVT.getVectorElementType(); Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, OperandEltVT, Operand, @@ -751,7 +745,7 @@ SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { } /// GetFPLibCall - Return the right libcall for the given floating point type. -static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, +static RTLIB::Libcall GetFPLibCall(MVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, @@ -780,10 +774,10 @@ PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { // with a "move to register" or "extload into register" instruction, then // permute it into place, if the idx is a constant and if the idx is // supported by the target. - MVT::ValueType VT = Tmp1.getValueType(); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); - MVT::ValueType IdxVT = Tmp3.getValueType(); - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT VT = Tmp1.getValueType(); + MVT EltVT = VT.getVectorElementType(); + MVT IdxVT = Tmp3.getValueType(); + MVT PtrVT = TLI.getPointerTy(); SDOperand StackPtr = DAG.CreateStackTemporary(VT); FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); @@ -798,7 +792,7 @@ PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); // Add the offset to the index. - unsigned EltSize = MVT::getSizeInBits(EltVT)/8; + unsigned EltSize = EltVT.getSizeInBits()/8; Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. @@ -911,7 +905,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = DAG.getConstant(0, TLI.getPointerTy()); break; case ISD::FRAME_TO_ARGS_OFFSET: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Custom: @@ -926,7 +920,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case ISD::EXCEPTIONADDR: { Tmp1 = LegalizeOp(Node->getOperand(0)); - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { @@ -961,7 +955,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::EHSELECTION: { Tmp1 = LegalizeOp(Node->getOperand(0)); Tmp2 = LegalizeOp(Node->getOperand(1)); - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { @@ -994,7 +988,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(Op.getValue(1), Tmp2); return Op.ResNo ? Tmp2 : Tmp1; case ISD::EH_RETURN: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // The only "good" option for this node is to custom lower it. switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported at all!"); @@ -1039,14 +1033,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); return Result.getValue(Op.ResNo); case ISD::UNDEF: { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); switch (TLI.getOperationAction(ISD::UNDEF, VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: - if (MVT::isInteger(VT)) + if (VT.isInteger()) Result = DAG.getConstant(0, VT); - else if (MVT::isFloatingPoint(VT)) - Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), + else if (VT.isFloatingPoint()) + Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), VT); else assert(0 && "Unknown value type!"); @@ -1454,13 +1448,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // SCALAR_TO_VECTOR requires that the type of the value being inserted // match the element type of the vector being created. if (Tmp2.getValueType() == - MVT::getVectorElementType(Op.getValueType())) { + Op.getValueType().getVectorElementType()) { SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, Tmp1.getValueType(), Tmp2); - unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); - MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); - MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); + unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); + MVT ShufMaskVT = + MVT::getIntVectorWithNumElements(NumElts); + MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); // We generate a shuffle of InVec and ScVec, so the shuffle mask // should be 0,1,2,3,4,5... with the appropriate element replaced with @@ -1531,9 +1526,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } // FALLTHROUGH case TargetLowering::Expand: { - MVT::ValueType VT = Node->getValueType(0); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT VT = Node->getValueType(0); + MVT EltVT = VT.getVectorElementType(); + MVT PtrVT = TLI.getPointerTy(); SDOperand Mask = Node->getOperand(2); unsigned NumElems = Mask.getNumOperands(); SmallVector<SDOperand,8> Ops; @@ -1557,8 +1552,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } case TargetLowering::Promote: { // Change base type to a different vector type. - MVT::ValueType OVT = Node->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + MVT OVT = Node->getValueType(0); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); // Cast the two input vectors. Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); @@ -1679,7 +1674,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); return Result.getValue(Op.ResNo); case ISD::DYNAMIC_STACKALLOC: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. @@ -1820,7 +1815,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SDOperand Table = Result.getOperand(1); SDOperand Index = Result.getOperand(2); - MVT::ValueType PTy = TLI.getPointerTy(); + MVT PTy = TLI.getPointerTy(); MachineFunction &MF = DAG.getMachineFunction(); unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); @@ -1939,7 +1934,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); Tmp3 = Result.getValue(0); Tmp4 = Result.getValue(1); @@ -1951,7 +1946,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); + getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, TLI); @@ -1971,9 +1966,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case TargetLowering::Promote: { // Only promote a load of vector type to another. - assert(MVT::isVector(VT) && "Cannot promote this load!"); + assert(VT.isVector() && "Cannot promote this load!"); // Change base type to a different vector type. - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), @@ -1989,13 +1984,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, 1), Tmp4); return Op.ResNo ? Tmp4 : Tmp3; } else { - MVT::ValueType SrcVT = LD->getMemoryVT(); - unsigned SrcWidth = MVT::getSizeInBits(SrcVT); + MVT SrcVT = LD->getMemoryVT(); + unsigned SrcWidth = SrcVT.getSizeInBits(); int SVOffset = LD->getSrcValueOffset(); unsigned Alignment = LD->getAlignment(); bool isVolatile = LD->isVolatile(); - if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) && + if (SrcWidth != SrcVT.getStoreSizeInBits() && // Some targets pretend to have an i1 loading operation, and actually // load an i8. This trick is correct for ZEXTLOAD because the top 7 // bits are guaranteed to be zero; it helps the optimizers understand @@ -2007,8 +2002,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { // Promote to a byte-sized load if not loading an integral number of // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. - unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT); - MVT::ValueType NVT = MVT::getIntegerType(NewWidth); + unsigned NewWidth = SrcVT.getStoreSizeInBits(); + MVT NVT = MVT::getIntegerVT(NewWidth); SDOperand Ch; // The extra bits are guaranteed to be zero, since we stored them that @@ -2036,7 +2031,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp2 = LegalizeOp(Ch); } else if (SrcWidth & (SrcWidth - 1)) { // If not loading a power-of-2 number of bits, expand as two loads. - assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) && + assert(SrcVT.isExtended() && !SrcVT.isVector() && "Unsupported extload!"); unsigned RoundWidth = 1 << Log2_32(SrcWidth); assert(RoundWidth < SrcWidth); @@ -2044,8 +2039,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { assert(ExtraWidth < RoundWidth); assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && "Load size not an integral number of bytes!"); - MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); - MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); + MVT RoundVT = MVT::getIntegerVT(RoundWidth); + MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); SDOperand Lo, Hi, Ch; unsigned IncrementSize; @@ -2130,7 +2125,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); + getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, TLI); @@ -2180,14 +2175,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } } case ISD::EXTRACT_ELEMENT: { - MVT::ValueType OpTy = Node->getOperand(0).getValueType(); + MVT OpTy = Node->getOperand(0).getValueType(); switch (getTypeAction(OpTy)) { default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); case Legal: if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { // 1 -> Hi Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), - DAG.getConstant(MVT::getSizeInBits(OpTy)/2, + DAG.getConstant(OpTy.getSizeInBits()/2, TLI.getShiftAmountTy())); Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); } else { @@ -2252,7 +2247,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); break; case Expand: - if (!MVT::isVector(Tmp2.getValueType())) { + if (!Tmp2.getValueType().isVector()) { SDOperand Lo, Hi; ExpandOp(Tmp2, Lo, Hi); @@ -2268,12 +2263,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } else { SDNode *InVal = Tmp2.Val; int InIx = Tmp2.ResNo; - unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); - MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); + unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); + MVT EVT = InVal->getValueType(InIx).getVectorElementType(); // Figure out if there is a simple type corresponding to this Vector // type. If so, convert to the vector type. - MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a return of the vector type. Tmp2 = LegalizeOp(Tmp2); @@ -2321,7 +2316,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case Expand: { SDOperand Lo, Hi; - assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && + assert(!Node->getOperand(i).getValueType().isExtended() && "FIXME: TODO: implement returning non-legal vector types!"); ExpandOp(Node->getOperand(i), Lo, Hi); NewValues.push_back(Lo); @@ -2417,7 +2412,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, ST->getOffset()); - MVT::ValueType VT = Tmp3.getValueType(); + MVT VT = Tmp3.getValueType(); switch (TLI.getOperationAction(ISD::STORE, VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Legal: @@ -2425,7 +2420,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); + getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); if (ST->getAlignment() < ABIAlignment) Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, TLI); @@ -2436,7 +2431,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { if (Tmp1.Val) Result = Tmp1; break; case TargetLowering::Promote: - assert(MVT::isVector(VT) && "Unknown legal promote case!"); + assert(VT.isVector() && "Unknown legal promote case!"); Tmp3 = DAG.getNode(ISD::BIT_CONVERT, TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); Result = DAG.getStore(Tmp1, Tmp3, Tmp2, @@ -2461,16 +2456,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // If this is a vector type, then we have to calculate the increment as // the product of the element size in bytes, and the number of elements // in the high half of the vector. - if (MVT::isVector(ST->getValue().getValueType())) { + if (ST->getValue().getValueType().isVector()) { SDNode *InVal = ST->getValue().Val; int InIx = ST->getValue().ResNo; - MVT::ValueType InVT = InVal->getValueType(InIx); - unsigned NumElems = MVT::getVectorNumElements(InVT); - MVT::ValueType EVT = MVT::getVectorElementType(InVT); + MVT InVT = InVal->getValueType(InIx); + unsigned NumElems = InVT.getVectorNumElements(); + MVT EVT = InVT.getVectorElementType(); // Figure out if there is a simple type corresponding to this Vector // type. If so, convert to the vector type. - MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a normal store of the vector type. Tmp3 = LegalizeOp(ST->getValue()); @@ -2489,12 +2484,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } else { SplitVectorOp(ST->getValue(), Lo, Hi); - IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * - MVT::getSizeInBits(EVT)/8; + IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * + EVT.getSizeInBits()/8; } } else { ExpandOp(ST->getValue(), Lo, Hi); - IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; + IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -2537,20 +2532,20 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SVOffset, MVT::i8, isVolatile, Alignment); } - MVT::ValueType StVT = ST->getMemoryVT(); - unsigned StWidth = MVT::getSizeInBits(StVT); + MVT StVT = ST->getMemoryVT(); + unsigned StWidth = StVT.getSizeInBits(); - if (StWidth != MVT::getStoreSizeInBits(StVT)) { + if (StWidth != StVT.getStoreSizeInBits()) { // Promote to a byte-sized store with upper bits zero if not // storing an integral number of bytes. For example, promote // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) - MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT)); + MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, NVT, isVolatile, Alignment); } else if (StWidth & (StWidth - 1)) { // If not storing a power-of-2 number of bits, expand as two stores. - assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) && + assert(StVT.isExtended() && !StVT.isVector() && "Unsupported truncstore!"); unsigned RoundWidth = 1 << Log2_32(StWidth); assert(RoundWidth < StWidth); @@ -2558,8 +2553,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { assert(ExtraWidth < RoundWidth); assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && "Store size not an integral number of bytes!"); - MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); - MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); + MVT RoundVT = MVT::getIntegerVT(RoundWidth); + MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); SDOperand Lo, Hi; unsigned IncrementSize; @@ -2612,7 +2607,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); + getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); if (ST->getAlignment() < ABIAlignment) Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, TLI); @@ -2761,13 +2756,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case TargetLowering::Promote: { - MVT::ValueType NVT = + MVT NVT = TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); unsigned ExtOp, TruncOp; - if (MVT::isVector(Tmp2.getValueType())) { + if (Tmp2.getValueType().isVector()) { ExtOp = ISD::BIT_CONVERT; TruncOp = ISD::BIT_CONVERT; - } else if (MVT::isInteger(Tmp2.getValueType())) { + } else if (Tmp2.getValueType().isInteger()) { ExtOp = ISD::ANY_EXTEND; TruncOp = ISD::TRUNCATE; } else { @@ -2847,23 +2842,23 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // First step, figure out the appropriate operation to use. // Allow SETCC to not be supported for all legal data types // Mostly this targets FP - MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); - MVT::ValueType OldVT = NewInTy; OldVT = OldVT; + MVT NewInTy = Node->getOperand(0).getValueType(); + MVT OldVT = NewInTy; OldVT = OldVT; // Scan for the appropriate larger type to use. while (1) { - NewInTy = (MVT::ValueType)(NewInTy+1); + NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); - assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && + assert(NewInTy.isInteger() == OldVT.isInteger() && "Fell off of the edge of the integer world"); - assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && + assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && "Fell off of the edge of the floating point world"); // If the target supports SETCC of this type, use it. if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) break; } - if (MVT::isInteger(NewInTy)) + if (NewInTy.isInteger()) assert(0 && "Cannot promote Legal Integer SETCC yet"); else { Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); @@ -2878,7 +2873,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: // Expand a setcc node into a select_cc of the same condition, lhs, and // rhs that selects between const 1 (true) and const 0 (false). - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); @@ -2983,7 +2978,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { if (Tmp1.Val) Result = Tmp1; break; case TargetLowering::Expand: { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); // See if multiply or divide can be lowered using two-result operations. SDVTList VTs = DAG.getVTList(VT, VT); @@ -3056,7 +3051,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } - assert(MVT::isVector(Node->getValueType(0)) && + assert(Node->getValueType(0).isVector() && "Cannot expand this binary operator!"); // Expand the operation into a bunch of nasty scalar code. Result = LegalizeOp(UnrollVectorOp(Op)); @@ -3068,9 +3063,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::AND: case ISD::OR: case ISD::XOR: { - MVT::ValueType OVT = Node->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); - assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); + MVT OVT = Node->getValueType(0); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + assert(OVT.isVector() && "Cannot promote this BinOp!"); // Bit convert each of the values to the new type. Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); @@ -3128,7 +3123,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == TargetLowering::Legal) { // Get the sign bit of the RHS. - MVT::ValueType IVT = + MVT IVT = Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), @@ -3146,7 +3141,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } // Otherwise, do bitwise ops! - MVT::ValueType NVT = + MVT NVT = Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); @@ -3180,7 +3175,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { return Result; case ISD::BUILD_PAIR: { - MVT::ValueType PairTy = Node->getValueType(0); + MVT PairTy = Node->getValueType(0); // TODO: handle the case where the Lo and Hi operands are not of legal type Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi @@ -3196,7 +3191,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, - DAG.getConstant(MVT::getSizeInBits(PairTy)/2, + DAG.getConstant(PairTy.getSizeInBits()/2, TLI.getShiftAmountTy())); Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); break; @@ -3225,7 +3220,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: { unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; bool isSigned = DivOpc == ISD::SDIV; - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // See if remainder can be lowered using two-result operations. SDVTList VTs = DAG.getVTList(VT, VT); @@ -3240,14 +3235,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } - if (MVT::isInteger(VT)) { + if (VT.isInteger()) { if (TLI.getOperationAction(DivOpc, VT) == TargetLowering::Legal) { // X % Y -> X-X/Y*Y Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); - } else if (MVT::isVector(VT)) { + } else if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); } else { assert(VT == MVT::i32 && @@ -3258,9 +3253,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = ExpandLibCall(LC, Node, isSigned, Dummy); } } else { - assert(MVT::isFloatingPoint(VT) && + assert(VT.isFloatingPoint() && "remainder op must have integer or floating-point type"); - if (MVT::isVector(VT)) { + if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); } else { // Floating point mod -> fmod libcall. @@ -3278,7 +3273,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Custom: @@ -3302,7 +3297,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, - DAG.getConstant(MVT::getSizeInBits(VT)/8, + DAG.getConstant(VT.getSizeInBits()/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); @@ -3420,9 +3415,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = DAG.UpdateNodeOperands(Result, Tmp1); break; case TargetLowering::Promote: { - MVT::ValueType OVT = Tmp1.getValueType(); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); - unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); + MVT OVT = Tmp1.getValueType(); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); @@ -3453,8 +3448,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case TargetLowering::Promote: { - MVT::ValueType OVT = Tmp1.getValueType(); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + MVT OVT = Tmp1.getValueType(); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); // Zero extend the argument. Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); @@ -3467,16 +3462,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::CTTZ: //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT), NVT), + DAG.getConstant(NVT.getSizeInBits(), NVT), ISD::SETEQ); Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, - DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); + DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); break; case ISD::CTLZ: // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) Result = DAG.getNode(ISD::SUB, NVT, Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT) - - MVT::getSizeInBits(OVT), NVT)); + DAG.getConstant(NVT.getSizeInBits() - + OVT.getSizeInBits(), NVT)); break; } break; @@ -3516,7 +3511,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case ISD::FABS: { // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Tmp2 = DAG.getConstantFP(0.0, VT); Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, ISD::SETUGT); @@ -3527,10 +3522,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::FSQRT: case ISD::FSIN: case ISD::FCOS: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // Expand unsupported unary vector operators by unrolling them. - if (MVT::isVector(VT)) { + if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); break; } @@ -3560,10 +3555,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case ISD::FPOWI: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // Expand unsupported unary vector operators by unrolling them. - if (MVT::isVector(VT)) { + if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); break; } @@ -3579,17 +3574,17 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { if (!isTypeLegal(Node->getOperand(0).getValueType())) { Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), Node->getValueType(0)); - } else if (MVT::isVector(Op.getOperand(0).getValueType())) { + } else if (Op.getOperand(0).getValueType().isVector()) { // The input has to be a vector type, we have to either scalarize it, pack // it, or convert it based on whether the input vector type is legal. SDNode *InVal = Node->getOperand(0).Val; int InIx = Node->getOperand(0).ResNo; - unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); - MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); + unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); + MVT EVT = InVal->getValueType(InIx).getVectorElementType(); // Figure out if there is a simple type corresponding to this Vector // type. If so, convert to the vector type. - MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a bit convert of the vector input. Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), @@ -3716,11 +3711,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: if (Node->getOpcode() == ISD::FP_TO_UINT) { SDOperand True, False; - MVT::ValueType VT = Node->getOperand(0).getValueType(); - MVT::ValueType NVT = Node->getValueType(0); + MVT VT = Node->getOperand(0).getValueType(); + MVT NVT = Node->getValueType(0); const uint64_t zero[] = {0, 0}; - APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); - APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT)); + APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); + APInt x = APInt::getSignBit(NVT.getSizeInBits()); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); Tmp2 = DAG.getConstantFP(apf, VT); Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), @@ -3740,8 +3735,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; case Expand: { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType OVT = Node->getOperand(0).getValueType(); + MVT VT = Op.getValueType(); + MVT OVT = Node->getOperand(0).getValueType(); // Convert ppcf128 to i32 if (OVT == MVT::ppcf128 && VT == MVT::i32) { if (Node->getOpcode() == ISD::FP_TO_SINT) { @@ -3858,8 +3853,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; case ISD::FP_EXTEND: { - MVT::ValueType DstVT = Op.getValueType(); - MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); + MVT DstVT = Op.getValueType(); + MVT SrcVT = Op.getOperand(0).getValueType(); if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { // The only other way we can lower this is to turn it into a STORE, // LOAD pair, targetting a temporary location (a stack slot). @@ -3880,8 +3875,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } case ISD::FP_ROUND: { - MVT::ValueType DstVT = Op.getValueType(); - MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); + MVT DstVT = Op.getValueType(); + MVT SrcVT = Op.getOperand(0).getValueType(); if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { if (SrcVT == MVT::ppcf128) { SDOperand Lo; @@ -3949,7 +3944,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::FP_ROUND_INREG: case ISD::SIGN_EXTEND_INREG: { Tmp1 = LegalizeOp(Node->getOperand(0)); - MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); + MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); // If this operation is not supported, convert it to a shl/shr or load/store // pair. @@ -3963,8 +3958,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { // NOTE: we could fall back on load/store here too for targets without // SAR. However, it is doubtful that any exist. - unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - - MVT::getSizeInBits(ExtraVT); + unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - + ExtraVT.getSizeInBits(); SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); Result = DAG.getNode(ISD::SHL, Node->getValueType(0), Node->getOperand(0), ShiftCst); @@ -4004,7 +3999,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { return Op.ResNo ? Tmp1 : Result; } case ISD::FLT_ROUNDS_: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action not supported for this op yet!"); case TargetLowering::Custom: @@ -4019,7 +4014,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { break; } case ISD::TRAP: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action not supported for this op yet!"); case TargetLowering::Legal: @@ -4064,11 +4059,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { /// have the correct bits for the low portion of the register, but no guarantee /// is made about the top bits: it may be zero, sign-extended, or garbage. SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = Op.getValueType(); + MVT NVT = TLI.getTypeToTransformTo(VT); assert(getTypeAction(VT) == Promote && "Caller should expand or legalize operands that are not promotable!"); - assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && + assert(NVT > VT && NVT.isInteger() == VT.isInteger() && "Cannot promote to smaller type!"); SDOperand Tmp1, Tmp2, Tmp3; @@ -4341,7 +4336,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { // These operators require that their input be sign extended. Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); - if (MVT::isInteger(NVT)) { + if (NVT.isInteger()) { Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, DAG.getValueType(VT)); Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, @@ -4350,7 +4345,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); // Perform FP_ROUND: this is probably overly pessimistic. - if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) + if (NVT.isFloatingPoint() && NoExcessFPPrecision) Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, DAG.getValueType(VT)); break; @@ -4381,7 +4376,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { // These operators require that their input be zero extended. Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); - assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); + assert(NVT.isInteger() && "Operators don't apply to FP!"); Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); @@ -4416,7 +4411,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, - DAG.getConstant(MVT::getSizeInBits(VT)/8, + DAG.getConstant(VT.getSizeInBits()/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); @@ -4445,7 +4440,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 - unsigned VT2 = Tmp2.getValueType(); + MVT VT2 = Tmp2.getValueType(); assert(VT2 == Tmp3.getValueType() && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); // Ensure that the resulting node is at least the same size as the operands' @@ -4465,8 +4460,8 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); Result = DAG.getNode(ISD::SRL, NVT, Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT) - - MVT::getSizeInBits(VT), + DAG.getConstant(NVT.getSizeInBits() - + VT.getSizeInBits(), TLI.getShiftAmountTy())); break; case ISD::CTPOP: @@ -4483,16 +4478,16 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { case ISD::CTTZ: // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT), NVT), + DAG.getConstant(NVT.getSizeInBits(), NVT), ISD::SETEQ); Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, - DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); + DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); break; case ISD::CTLZ: //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) Result = DAG.getNode(ISD::SUB, NVT, Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT) - - MVT::getSizeInBits(VT), NVT)); + DAG.getConstant(NVT.getSizeInBits() - + VT.getSizeInBits(), NVT)); break; } break; @@ -4525,8 +4520,8 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { SDOperand Vec = Op.getOperand(0); SDOperand Idx = Op.getOperand(1); - MVT::ValueType TVT = Vec.getValueType(); - unsigned NumElems = MVT::getVectorNumElements(TVT); + MVT TVT = Vec.getValueType(); + unsigned NumElems = TVT.getVectorNumElements(); switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { default: assert(0 && "This action is not supported yet!"); @@ -4575,12 +4570,11 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); // Add the offset to the index. - unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; + unsigned EltSize = Op.getValueType().getSizeInBits()/8; Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, DAG.getConstant(EltSize, Idx.getValueType())); - if (MVT::getSizeInBits(Idx.getValueType()) > - MVT::getSizeInBits(TLI.getPointerTy())) + if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits()) Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); else Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); @@ -4600,9 +4594,9 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { SDOperand Vec = Op.getOperand(0); SDOperand Idx = LegalizeOp(Op.getOperand(1)); - unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); + unsigned NumElems = Vec.getValueType().getVectorNumElements(); - if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { + if (NumElems == Op.getValueType().getVectorNumElements()) { // This must be an access of the desired vector length. Return it. return Vec; } @@ -4643,9 +4637,9 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, Tmp2 = PromoteOp(RHS); // RHS // If this is an FP compare, the operands have already been extended. - if (MVT::isInteger(LHS.getValueType())) { - MVT::ValueType VT = LHS.getValueType(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + if (LHS.getValueType().isInteger()) { + MVT VT = LHS.getValueType(); + MVT NVT = TLI.getTypeToTransformTo(VT); // Otherwise, we have to insert explicit sign or zero extends. Note // that we could insert sign extends for ALL conditions, but zero extend @@ -4678,7 +4672,7 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, } break; case Expand: { - MVT::ValueType VT = LHS.getValueType(); + MVT VT = LHS.getValueType(); if (VT == MVT::f32 || VT == MVT::f64) { // Expand into one or more soft-fp libcall(s). RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; @@ -4881,17 +4875,17 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, /// a load from the stack slot to DestVT, extending it if needed. /// The resultant code need not be legal. SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, - MVT::ValueType SlotVT, - MVT::ValueType DestVT) { + MVT SlotVT, + MVT DestVT) { // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); int SPFI = StackPtrFI->getIndex(); - unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); - unsigned SlotSize = MVT::getSizeInBits(SlotVT); - unsigned DestSize = MVT::getSizeInBits(DestVT); + unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); + unsigned SlotSize = SlotVT.getSizeInBits(); + unsigned DestSize = DestVT.getSizeInBits(); // Emit a store to the stack slot. Use a truncstore if the input value is // later than DestVT. @@ -4904,7 +4898,7 @@ SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, assert(SrcSize == SlotSize && "Invalid store"); Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, PseudoSourceValue::getFixedStack(), - SPFI, SlotVT); + SPFI); } // Result is a load from the stack slot. @@ -4975,7 +4969,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { // If all elements are constants, create a load from the constant pool. if (isConstant) { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); std::vector<Constant*> CV; for (unsigned i = 0, e = NumElems; i != e; ++i) { if (ConstantFPSDNode *V = @@ -4987,7 +4981,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { } else { assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); const Type *OpNTy = - MVT::getTypeForValueType(Node->getOperand(0).getValueType()); + Node->getOperand(0).getValueType().getTypeForMVT(); CV.push_back(UndefValue::get(OpNTy)); } } @@ -4999,9 +4993,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { if (SplatValue.Val) { // Splat of one value? // Build the shuffle constant vector: <0, 0, 0, 0> - MVT::ValueType MaskVT = - MVT::getIntVectorWithNumElements(NumElems); - SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); std::vector<SDOperand> ZeroVec(NumElems, Zero); SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &ZeroVec[0], ZeroVec.size()); @@ -5037,8 +5030,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { std::swap(Val1, Val2); // Build the shuffle constant vector: e.g. <0, 4, 0, 4> - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT MaskEltVT = MaskVT.getVectorElementType(); std::vector<SDOperand> MaskVec(NumElems); // Set elements of the shuffle mask for Val1. @@ -5072,14 +5065,13 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { // Otherwise, we can't handle this case efficiently. Allocate a sufficiently // aligned object on the stack, store each element into it, then load // the result as a vector. - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(VT); // Emit a store of each element to the stack slot. SmallVector<SDOperand, 8> Stores; - unsigned TypeByteSize = - MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; + unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; // Store (in the right endianness) the elements to memory. for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { // Ignore undef elements. @@ -5113,7 +5105,7 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, ExpandOp(Op, LHSL, LHSH); SDOperand Ops[] = { LHSL, LHSH, Amt }; - MVT::ValueType VT = LHSL.getValueType(); + MVT VT = LHSL.getValueType(); Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); Hi = Lo.getValue(1); } @@ -5128,12 +5120,12 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && "This is not a shift!"); - MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); + MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); SDOperand ShAmt = LegalizeOp(Amt); - MVT::ValueType ShTy = ShAmt.getValueType(); - unsigned ShBits = MVT::getSizeInBits(ShTy); - unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); - unsigned NVTBits = MVT::getSizeInBits(NVT); + MVT ShTy = ShAmt.getValueType(); + unsigned ShBits = ShTy.getSizeInBits(); + unsigned VTBits = Op.getValueType().getSizeInBits(); + unsigned NVTBits = NVT.getSizeInBits(); // Handle the case when Amt is an immediate. if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { @@ -5284,8 +5276,8 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { - MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); - const Type *ArgTy = MVT::getTypeForValueType(ArgVT); + MVT ArgVT = Node->getOperand(i).getValueType(); + const Type *ArgTy = ArgVT.getTypeForMVT(); Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; Entry.isSExt = isSigned; Entry.isZExt = !isSigned; @@ -5295,7 +5287,7 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, TLI.getPointerTy()); // Splice the libcall in wherever FindInputOutputChains tells us to. - const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); + const Type *RetTy = Node->getValueType(0).getTypeForMVT(); std::pair<SDOperand,SDOperand> CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, false, Callee, Args, DAG); @@ -5321,8 +5313,8 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, /// ExpandIntToFP - Expand a [US]INT_TO_FP operation. /// SDOperand SelectionDAGLegalize:: -ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { - MVT::ValueType SourceVT = Source.getValueType(); +ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) { + MVT SourceVT = Source.getValueType(); bool ExpandSource = getTypeAction(SourceVT) == Expand; // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. @@ -5360,7 +5352,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { if (DestTy == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0); - else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) + else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits()) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), CPIdx, @@ -5369,12 +5361,12 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { else assert(0 && "Unexpected conversion"); - MVT::ValueType SCVT = SignedConv.getValueType(); + MVT SCVT = SignedConv.getValueType(); if (SCVT != DestTy) { // Destination type needs to be expanded as well. The FADD now we are // constructing will be expanded into a libcall. - if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { - assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy)); + if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { + assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, SignedConv, SignedConv.getValue(1)); } @@ -5455,7 +5447,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { /// legal for the target. SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDOperand Op0, - MVT::ValueType DestVT) { + MVT DestVT) { if (Op0.getValueType() == MVT::i32) { // simple 32-bit [signed|unsigned] integer to float/double expansion @@ -5501,10 +5493,12 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, if (DestVT == MVT::f64) { // do nothing Result = Sub; - } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { + } else if (DestVT.getSizeInBits() < + MVT(MVT::f64).getSizeInBits()) { Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, DAG.getIntPtrConstant(0)); - } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { + } else if (DestVT.getSizeInBits() > + MVT(MVT::f64).getSizeInBits()) { Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); } return Result; @@ -5523,7 +5517,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, // as a negative number. To counteract this, the dynamic code adds an // offset depending on the data type. uint64_t FF; - switch (Op0.getValueType()) { + switch (Op0.getValueType().getSimpleVT()) { default: assert(0 && "Unsupported integer type!"); case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) @@ -5556,17 +5550,17 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP /// operation that takes a larger input. SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, - MVT::ValueType DestVT, + MVT DestVT, bool isSigned) { // First step, figure out the appropriate *INT_TO_FP operation to use. - MVT::ValueType NewInTy = LegalOp.getValueType(); + MVT NewInTy = LegalOp.getValueType(); unsigned OpToUse = 0; // Scan for the appropriate larger type to use. while (1) { - NewInTy = (MVT::ValueType)(NewInTy+1); - assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); + NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); + assert(NewInTy.isInteger() && "Ran out of possibilities!"); // If the target supports SINT_TO_FP of this type, use it. switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { @@ -5611,17 +5605,17 @@ SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT /// operation that returns a larger result. SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, - MVT::ValueType DestVT, + MVT DestVT, bool isSigned) { // First step, figure out the appropriate FP_TO*INT operation to use. - MVT::ValueType NewOutTy = DestVT; + MVT NewOutTy = DestVT; unsigned OpToUse = 0; // Scan for the appropriate larger type to use. while (1) { - NewOutTy = (MVT::ValueType)(NewOutTy+1); - assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); + NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); + assert(NewOutTy.isInteger() && "Ran out of possibilities!"); // If the target supports FP_TO_SINT returning this type, use it. switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { @@ -5672,10 +5666,10 @@ SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. /// SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType SHVT = TLI.getShiftAmountTy(); + MVT VT = Op.getValueType(); + MVT SHVT = TLI.getShiftAmountTy(); SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; - switch (VT) { + switch (VT.getSimpleVT()) { default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); case MVT::i16: Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); @@ -5727,9 +5721,9 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL }; - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType ShVT = TLI.getShiftAmountTy(); - unsigned len = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + MVT ShVT = TLI.getShiftAmountTy(); + unsigned len = VT.getSizeInBits(); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) SDOperand Tmp2 = DAG.getConstant(mask[i], VT); @@ -5750,9 +5744,9 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { // return popcount(~x); // // but see also: http://www.hackersdelight.org/HDcode/nlz.cc - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType ShVT = TLI.getShiftAmountTy(); - unsigned len = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + MVT ShVT = TLI.getShiftAmountTy(); + unsigned len = VT.getSizeInBits(); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); @@ -5765,7 +5759,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { // unless the target has ctlz but not ctpop, in which case we use: // { return 32 - nlz(~x & (x-1)); } // see also http://www.hackersdelight.org/HDcode/ntz.cc - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::XOR, VT, Op, Tmp2), @@ -5774,7 +5768,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { if (!TLI.isOperationLegal(ISD::CTPOP, VT) && TLI.isOperationLegal(ISD::CTLZ, VT)) return DAG.getNode(ISD::SUB, VT, - DAG.getConstant(MVT::getSizeInBits(VT), VT), + DAG.getConstant(VT.getSizeInBits(), VT), DAG.getNode(ISD::CTLZ, VT, Tmp3)); return DAG.getNode(ISD::CTPOP, VT, Tmp3); } @@ -5787,13 +5781,12 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { /// ExpandedNodes map is filled in for any results that are expanded, and the /// Lo/Hi values are returned. void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = Op.getValueType(); + MVT NVT = TLI.getTypeToTransformTo(VT); SDNode *Node = Op.Val; assert(getTypeAction(VT) == Expand && "Not an expanded type!"); - assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || - MVT::isVector(VT)) && - "Cannot expand to FP value or to larger int value!"); + assert(((NVT.isInteger() && NVT < VT) || VT.isFloatingPoint() || + VT.isVector()) && "Cannot expand to FP value or to larger int value!"); // See if we already expanded it. DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I @@ -5844,7 +5837,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ Hi = DAG.getNode(ISD::UNDEF, NVT); break; case ISD::Constant: { - unsigned NVTBits = MVT::getSizeInBits(NVT); + unsigned NVTBits = NVT.getSizeInBits(); const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); @@ -5893,7 +5886,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ // The high part gets the sign extension from the lo-part. This handles // things like sextinreg V:i64 from i8. Hi = DAG.getNode(ISD::SRA, NVT, Lo, - DAG.getConstant(MVT::getSizeInBits(NVT)-1, + DAG.getConstant(NVT.getSizeInBits()-1, TLI.getShiftAmountTy())); break; @@ -5916,7 +5909,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ case ISD::CTLZ: { // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) ExpandOp(Node->getOperand(0), Lo, Hi); - SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); + SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, ISD::SETNE); @@ -5931,7 +5924,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ case ISD::CTTZ: { // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) ExpandOp(Node->getOperand(0), Lo, Hi); - SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); + SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, ISD::SETNE); @@ -5980,7 +5973,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ } // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; + unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); SVOffset += IncrementSize; @@ -5998,7 +5991,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ if (TLI.isBigEndian()) std::swap(Lo, Hi); } else { - MVT::ValueType EVT = LD->getMemoryVT(); + MVT EVT = LD->getMemoryVT(); if ((VT == MVT::f64 && EVT == MVT::f32) || (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { @@ -6025,7 +6018,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ if (ExtType == ISD::SEXTLOAD) { // The high part is obtained by SRA'ing all but one of the bits of the // lo part. - unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); + unsigned LoSize = Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else if (ExtType == ISD::ZEXTLOAD) { @@ -6085,7 +6078,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ // The high part is obtained by SRA'ing all but one of the bits of the lo // part. - unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); + unsigned LoSize = Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); break; @@ -6134,7 +6127,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ // If source operand will be expanded to the same type as VT, i.e. // i64 <- f64, i32 <- f32, expand the source operand instead. - MVT::ValueType VT0 = Node->getOperand(0).getValueType(); + MVT VT0 = Node->getOperand(0).getValueType(); if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { ExpandOp(Node->getOperand(0), Lo, Hi); break; @@ -6668,7 +6661,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: { bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; - MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); + MVT SrcVT = Node->getOperand(0).getValueType(); // Promote the operand if needed. Do this before checking for // ppcf128 so conversions of i16 and i8 work. @@ -6753,18 +6746,18 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ /// two smaller values, still of vector type. void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) { - assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); + assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); SDNode *Node = Op.Val; - unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); + unsigned NumElements = Op.getValueType().getVectorNumElements(); assert(NumElements > 1 && "Cannot split a single element vector!"); - MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); + MVT NewEltVT = Op.getValueType().getVectorElementType(); unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; - MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); - MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); + MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); + MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); // See if we already split it. std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I @@ -6812,7 +6805,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, // Build the low part. SDOperand Mask = Node->getOperand(2); SmallVector<SDOperand, 8> Ops; - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT PtrVT = TLI.getPointerTy(); // Insert all of the elements from the input that are needed. We use // buildvector of extractelement here because the input vectors will have @@ -6887,7 +6880,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, SplitVectorOp(Node->getOperand(1), LL, LH); SplitVectorOp(Node->getOperand(2), RL, RH); - if (MVT::isVector(Cond.getValueType())) { + if (Cond.getValueType().isVector()) { // Handle a vector merge. SDOperand CL, CH; SplitVectorOp(Cond, CL, CH); @@ -6969,7 +6962,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, bool isVolatile = LD->isVolatile(); Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); - unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; + unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); SVOffset += IncrementSize; @@ -6989,8 +6982,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, // We know the result is a vector. The input may be either a vector or a // scalar value. SDOperand InOp = Node->getOperand(0); - if (!MVT::isVector(InOp.getValueType()) || - MVT::getVectorNumElements(InOp.getValueType()) == 1) { + if (!InOp.getValueType().isVector() || + InOp.getValueType().getVectorNumElements() == 1) { // The input is a scalar or single-element vector. // Lower to a store/load so that it can be split. // FIXME: this could be improved probably. @@ -7024,11 +7017,10 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, /// (e.g. v1f32), convert it into the equivalent operation that returns a /// scalar (e.g. f32) value. SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { - assert(MVT::isVector(Op.getValueType()) && - "Bad ScalarizeVectorOp invocation!"); + assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); SDNode *Node = Op.Val; - MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); - assert(MVT::getVectorNumElements(Op.getValueType()) == 1); + MVT NewVT = Op.getValueType().getVectorElementType(); + assert(Op.getValueType().getVectorNumElements() == 1); // See if we already scalarized it. std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); @@ -7118,7 +7110,7 @@ SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { break; case ISD::BIT_CONVERT: { SDOperand Op0 = Op.getOperand(0); - if (MVT::getVectorNumElements(Op0.getValueType()) == 1) + if (Op0.getValueType().getVectorNumElements() == 1) Op0 = ScalarizeVectorOp(Op0); Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); break; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index c0cfe216bfe..61d0e451622 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -68,7 +68,7 @@ void DAGTypeLegalizer::run() { unsigned i = 0; unsigned NumResults = N->getNumValues(); do { - MVT::ValueType ResultVT = N->getValueType(i); + MVT ResultVT = N->getValueType(i); switch (getTypeAction(ResultVT)) { default: assert(false && "Unknown action!"); @@ -98,7 +98,7 @@ void DAGTypeLegalizer::run() { unsigned NumOperands = N->getNumOperands(); bool NeedsRevisit = false; for (i = 0; i != NumOperands; ++i) { - MVT::ValueType OpVT = N->getOperand(i).getValueType(); + MVT OpVT = N->getOperand(i).getValueType(); switch (getTypeAction(OpVT)) { default: assert(false && "Unknown action!"); @@ -472,13 +472,12 @@ void DAGTypeLegalizer::SetSplitOp(SDOperand Op, SDOperand Lo, SDOperand Hi) { /// BitConvertToInteger - Convert to an integer of the same size. SDOperand DAGTypeLegalizer::BitConvertToInteger(SDOperand Op) { - return DAG.getNode(ISD::BIT_CONVERT, - MVT::getIntegerType(MVT::getSizeInBits(Op.getValueType())), - Op); + unsigned BitWidth = Op.getValueType().getSizeInBits(); + return DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerVT(BitWidth), Op); } SDOperand DAGTypeLegalizer::CreateStackStoreLoad(SDOperand Op, - MVT::ValueType DestVT) { + MVT DestVT) { // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(DestVT); @@ -490,14 +489,13 @@ SDOperand DAGTypeLegalizer::CreateStackStoreLoad(SDOperand Op, /// JoinIntegers - Build an integer with low bits Lo and high bits Hi. SDOperand DAGTypeLegalizer::JoinIntegers(SDOperand Lo, SDOperand Hi) { - MVT::ValueType LVT = Lo.getValueType(); - MVT::ValueType HVT = Hi.getValueType(); - MVT::ValueType NVT = MVT::getIntegerType(MVT::getSizeInBits(LVT) + - MVT::getSizeInBits(HVT)); + MVT LVT = Lo.getValueType(); + MVT HVT = Hi.getValueType(); + MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits()); Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Lo); Hi = DAG.getNode(ISD::ANY_EXTEND, NVT, Hi); - Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(MVT::getSizeInBits(LVT), + Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(LVT.getSizeInBits(), TLI.getShiftAmountTy())); return DAG.getNode(ISD::OR, NVT, Lo, Hi); } @@ -505,13 +503,13 @@ SDOperand DAGTypeLegalizer::JoinIntegers(SDOperand Lo, SDOperand Hi) { /// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT /// bits in Hi. void DAGTypeLegalizer::SplitInteger(SDOperand Op, - MVT::ValueType LoVT, MVT::ValueType HiVT, + MVT LoVT, MVT HiVT, SDOperand &Lo, SDOperand &Hi) { - assert(MVT::getSizeInBits(LoVT) + MVT::getSizeInBits(HiVT) == - MVT::getSizeInBits(Op.getValueType()) && "Invalid integer splitting!"); + assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() == + Op.getValueType().getSizeInBits() && "Invalid integer splitting!"); Lo = DAG.getNode(ISD::TRUNCATE, LoVT, Op); Hi = DAG.getNode(ISD::SRL, Op.getValueType(), Op, - DAG.getConstant(MVT::getSizeInBits(LoVT), + DAG.getConstant(LoVT.getSizeInBits(), TLI.getShiftAmountTy())); Hi = DAG.getNode(ISD::TRUNCATE, HiVT, Hi); } @@ -520,14 +518,13 @@ void DAGTypeLegalizer::SplitInteger(SDOperand Op, /// half the size of Op's. void DAGTypeLegalizer::SplitInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType HalfVT = - MVT::getIntegerType(MVT::getSizeInBits(Op.getValueType())/2); + MVT HalfVT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()/2); SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); } /// MakeLibCall - Generate a libcall taking the given operands as arguments and /// returning a result of type RetVT. -SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT, +SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT, const SDOperand *Ops, unsigned NumOps, bool isSigned) { TargetLowering::ArgListTy Args; @@ -536,7 +533,7 @@ SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT, TargetLowering::ArgListEntry Entry; for (unsigned i = 0; i != NumOps; ++i) { Entry.Node = Ops[i]; - Entry.Ty = MVT::getTypeForValueType(Entry.Node.getValueType()); + Entry.Ty = Entry.Node.getValueType().getTypeForMVT(); Entry.isSExt = isSigned; Entry.isZExt = !isSigned; Args.push_back(Entry); @@ -544,7 +541,7 @@ SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT, SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), TLI.getPointerTy()); - const Type *RetTy = MVT::getTypeForValueType(RetVT); + const Type *RetTy = RetVT.getTypeForMVT(); std::pair<SDOperand,SDOperand> CallInfo = TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, CallingConv::C, false, Callee, Args, DAG); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index a983c95cb68..db9adc619e3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -77,7 +77,7 @@ private: /// we need to expand it into multiple registers of a smaller integer type, or /// we need to scalarize a one-element vector type into the element type, or /// we need to split a vector type into smaller vector types. - LegalizeAction getTypeAction(MVT::ValueType VT) const { + LegalizeAction getTypeAction(MVT VT) const { switch (ValueTypeActions.getTypeAction(VT)) { default: assert(false && "Unknown legalize action!"); @@ -89,13 +89,12 @@ private: // Expand can mean // 1) split scalar in half, 2) convert a float to an integer, // 3) scalarize a single-element vector, 4) split a vector in two. - if (!MVT::isVector(VT)) { - if (MVT::getSizeInBits(VT) == - MVT::getSizeInBits(TLI.getTypeToTransformTo(VT))) + if (!VT.isVector()) { + if (VT.getSizeInBits() == TLI.getTypeToTransformTo(VT).getSizeInBits()) return FloatToInt; else return Expand; - } else if (MVT::getVectorNumElements(VT) == 1) { + } else if (VT.getVectorNumElements() == 1) { return Scalarize; } else { return Split; @@ -104,7 +103,7 @@ private: } /// isTypeLegal - Return true if this type is legal on this target. - bool isTypeLegal(MVT::ValueType VT) const { + bool isTypeLegal(MVT VT) const { return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal; } @@ -164,12 +163,12 @@ private: // Common routines. SDOperand BitConvertToInteger(SDOperand Op); - SDOperand CreateStackStoreLoad(SDOperand Op, MVT::ValueType DestVT); + SDOperand CreateStackStoreLoad(SDOperand Op, MVT DestVT); SDOperand JoinIntegers(SDOperand Lo, SDOperand Hi); void SplitInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi); - void SplitInteger(SDOperand Op, MVT::ValueType LoVT, MVT::ValueType HiVT, + void SplitInteger(SDOperand Op, MVT LoVT, MVT HiVT, SDOperand &Lo, SDOperand &Hi); - SDOperand MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT, + SDOperand MakeLibCall(RTLIB::Libcall LC, MVT RetVT, const SDOperand *Ops, unsigned NumOps, bool isSigned); //===--------------------------------------------------------------------===// @@ -187,7 +186,7 @@ private: /// GetPromotedZExtOp - Get a promoted operand and zero extend it to the final /// size. SDOperand GetPromotedZExtOp(SDOperand Op) { - MVT::ValueType OldVT = Op.getValueType(); + MVT OldVT = Op.getValueType(); Op = GetPromotedOp(Op); return DAG.getZeroExtendInReg(Op, OldVT); } @@ -292,10 +291,10 @@ private: SDOperand ExpandOperand_BUILD_VECTOR(SDNode *N); SDOperand ExpandOperand_EXTRACT_ELEMENT(SDNode *N); SDOperand ExpandOperand_SETCC(SDNode *N); - SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT::ValueType DestTy); + SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT DestTy); SDOperand ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo); SDOperand ExpandOperand_TRUNCATE(SDNode *N); - SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT::ValueType DestTy); + SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT DestTy); void ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS, ISD::CondCode &CCCode); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp index a07ef782cdb..29464248cee 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp @@ -105,14 +105,14 @@ void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) { void DAGTypeLegalizer::ExpandResult_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); Lo = Hi = DAG.getNode(ISD::UNDEF, NVT); } void DAGTypeLegalizer::ExpandResult_Constant(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - unsigned NBitWidth = MVT::getSizeInBits(NVT); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + unsigned NBitWidth = NVT.getSizeInBits(); const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); @@ -148,9 +148,9 @@ void DAGTypeLegalizer::ExpandResult_MERGE_VALUES(SDNode *N, void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) { + if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { // The low part is any extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. @@ -169,9 +169,9 @@ void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N, void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) { + if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { // The low part is zero extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); Hi = DAG.getConstant(0, NVT); // The high part is just a zero. @@ -186,20 +186,20 @@ void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N, // Split the promoted operand. This will simplify when it is expanded. SplitInteger(Res, Lo, Hi); unsigned ExcessBits = - MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT); - Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerType(ExcessBits)); + Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); + Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); } } void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) { + if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { // The low part is sign extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); // The high part is obtained by SRA'ing all but one of the bits of low part. - unsigned LoSize = MVT::getSizeInBits(NVT); + unsigned LoSize = NVT.getSizeInBits(); Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else { @@ -213,23 +213,23 @@ void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N, // Split the promoted operand. This will simplify when it is expanded. SplitInteger(Res, Lo, Hi); unsigned ExcessBits = - MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT); + Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, - DAG.getValueType(MVT::getIntegerType(ExcessBits))); + DAG.getValueType(MVT::getIntegerVT(ExcessBits))); } } void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N, SDOperand &Lo, SDOperand &Hi) { GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType NVT = Lo.getValueType(); - MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); - unsigned NVTBits = MVT::getSizeInBits(NVT); - unsigned EVTBits = MVT::getSizeInBits(EVT); + MVT NVT = Lo.getValueType(); + MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + unsigned NVTBits = NVT.getSizeInBits(); + unsigned EVTBits = EVT.getSizeInBits(); if (NVTBits < EVTBits) { Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, - DAG.getValueType(MVT::getIntegerType(EVTBits - NVTBits))); + DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); } else { Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); // The high part must be zero, make it explicit. @@ -239,19 +239,19 @@ void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N, void DAGTypeLegalizer::ExpandResult_TRUNCATE(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), - DAG.getConstant(MVT::getSizeInBits(NVT), + DAG.getConstant(NVT.getSizeInBits(), TLI.getShiftAmountTy())); Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); } void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand InOp = N->getOperand(0); - MVT::ValueType InVT = InOp.getValueType(); + MVT InVT = InOp.getValueType(); // Handle some special cases efficiently. switch (getTypeAction(InVT)) { @@ -299,9 +299,9 @@ void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N, void DAGTypeLegalizer:: ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) { GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); - if (MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(Lo.getValueType())) { + if (EVT.getSizeInBits() <= Lo.getValueType().getSizeInBits()) { // sext_inreg the low part if needed. Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, N->getOperand(1)); @@ -309,21 +309,21 @@ ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // The high part gets the sign extension from the lo-part. This handles // things like sextinreg V:i64 from i8. Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, - DAG.getConstant(MVT::getSizeInBits(Hi.getValueType())-1, + DAG.getConstant(Hi.getValueType().getSizeInBits()-1, TLI.getShiftAmountTy())); } else { // For example, extension of an i48 to an i64. Leave the low part alone, // sext_inreg the high part. unsigned ExcessBits = - MVT::getSizeInBits(EVT) - MVT::getSizeInBits(Lo.getValueType()); + EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, - DAG.getValueType(MVT::getIntegerType(ExcessBits))); + DAG.getValueType(MVT::getIntegerVT(ExcessBits))); } } void DAGTypeLegalizer::ExpandResult_FP_TO_SINT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); SDOperand Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (VT == MVT::i64) { @@ -352,7 +352,7 @@ void DAGTypeLegalizer::ExpandResult_FP_TO_SINT(SDNode *N, SDOperand &Lo, void DAGTypeLegalizer::ExpandResult_FP_TO_UINT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); SDOperand Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (VT == MVT::i64) { @@ -382,8 +382,8 @@ void DAGTypeLegalizer::ExpandResult_FP_TO_UINT(SDNode *N, SDOperand &Lo, void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi) { // FIXME: Add support for indexed loads. - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); SDOperand Ch = N->getChain(); // Legalize the chain. SDOperand Ptr = N->getBasePtr(); // Legalize the pointer. ISD::LoadExtType ExtType = N->getExtensionType(); @@ -391,13 +391,13 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, unsigned Alignment = N->getAlignment(); bool isVolatile = N->isVolatile(); - assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!"); + assert(!(NVT.getSizeInBits() & 7) && "Expanded type not byte sized!"); if (ExtType == ISD::NON_EXTLOAD) { Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, isVolatile, Alignment); // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize, @@ -411,8 +411,8 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, // Handle endianness of the load. if (TLI.isBigEndian()) std::swap(Lo, Hi); - } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) { - MVT::ValueType EVT = N->getMemoryVT(); + } else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) { + MVT EVT = N->getMemoryVT(); Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, isVolatile, Alignment); @@ -423,7 +423,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, if (ExtType == ISD::SEXTLOAD) { // The high part is obtained by SRA'ing all but one of the bits of the // lo part. - unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); + unsigned LoSize = Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else if (ExtType == ISD::ZEXTLOAD) { @@ -440,11 +440,11 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, isVolatile, Alignment); unsigned ExcessBits = - MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT); - MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits); + N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); + MVT NEVT = MVT::getIntegerVT(ExcessBits); // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), @@ -458,14 +458,14 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, } else { // Big-endian - high bits are at low addresses. Favor aligned loads at // the cost of some bit-fiddling. - MVT::ValueType EVT = N->getMemoryVT(); - unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8; - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + MVT EVT = N->getMemoryVT(); + unsigned EBytes = EVT.getStoreSizeInBits()/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; unsigned ExcessBits = (EBytes - IncrementSize)*8; // Load both the high bits and maybe some of the low bits. Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, - MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits), + MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), isVolatile, Alignment); // Increment the pointer to the other half. @@ -473,7 +473,8 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, DAG.getIntPtrConstant(IncrementSize)); // Load the rest of the low bits. Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), - SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits), + SVOffset+IncrementSize, + MVT::getIntegerVT(ExcessBits), isVolatile, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the @@ -481,7 +482,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), Hi.getValue(1)); - if (ExcessBits < MVT::getSizeInBits(NVT)) { + if (ExcessBits < NVT.getSizeInBits()) { // Transfer low bits from the bottom of Hi to the top of Lo. Lo = DAG.getNode(ISD::OR, NVT, Lo, DAG.getNode(ISD::SHL, NVT, Hi, @@ -489,7 +490,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, TLI.getShiftAmountTy()))); // Move high bits to the right position in Hi. Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, - DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits, + DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getShiftAmountTy())); } } @@ -602,8 +603,8 @@ void DAGTypeLegalizer::ExpandResult_ADDSUBE(SDNode *N, void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); @@ -613,8 +614,8 @@ void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N, SDOperand LL, LH, RL, RH; GetExpandedOp(N->getOperand(0), LL, LH); GetExpandedOp(N->getOperand(1), RL, RH); - unsigned OuterBitSize = MVT::getSizeInBits(VT); - unsigned BitSize = MVT::getSizeInBits(NVT); + unsigned OuterBitSize = VT.getSizeInBits(); + unsigned BitSize = NVT.getSizeInBits(); unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); @@ -705,7 +706,7 @@ void DAGTypeLegalizer::ExpandResult_UREM(SDNode *N, void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // If we can emit an efficient shift operation, do so now. Check to see if // the RHS is a constant. @@ -730,7 +731,7 @@ void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N, // Next check to see if the target supports this SHL_PARTS operation or if it // will custom expand it. - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT NVT = TLI.getTypeToTransformTo(VT); TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || Action == TargetLowering::Custom) { @@ -739,7 +740,7 @@ void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N, GetExpandedOp(N->getOperand(0), LHSL, LHSH); SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) }; - MVT::ValueType VT = LHSL.getValueType(); + MVT VT = LHSL.getValueType(); Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); Hi = Lo.getValue(1); return; @@ -770,7 +771,7 @@ void DAGTypeLegalizer::ExpandResult_CTLZ(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType NVT = Lo.getValueType(); + MVT NVT = Lo.getValueType(); SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, DAG.getConstant(0, NVT), ISD::SETNE); @@ -780,7 +781,7 @@ void DAGTypeLegalizer::ExpandResult_CTLZ(SDNode *N, Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, DAG.getNode(ISD::ADD, NVT, LoLZ, - DAG.getConstant(MVT::getSizeInBits(NVT), NVT))); + DAG.getConstant(NVT.getSizeInBits(), NVT))); Hi = DAG.getConstant(0, NVT); } @@ -788,7 +789,7 @@ void DAGTypeLegalizer::ExpandResult_CTPOP(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType NVT = Lo.getValueType(); + MVT NVT = Lo.getValueType(); Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), DAG.getNode(ISD::CTPOP, NVT, Hi)); Hi = DAG.getConstant(0, NVT); @@ -798,7 +799,7 @@ void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType NVT = Lo.getValueType(); + MVT NVT = Lo.getValueType(); SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, DAG.getConstant(0, NVT), ISD::SETNE); @@ -808,7 +809,7 @@ void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N, Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, DAG.getNode(ISD::ADD, NVT, HiLZ, - DAG.getConstant(MVT::getSizeInBits(NVT), NVT))); + DAG.getConstant(NVT.getSizeInBits(), NVT))); Hi = DAG.getConstant(0, NVT); } @@ -816,25 +817,24 @@ void DAGTypeLegalizer::ExpandResult_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { SDOperand OldVec = N->getOperand(0); - unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType()); + unsigned OldElts = OldVec.getValueType().getVectorNumElements(); // Convert to a vector of the expanded element type, for example // <2 x i64> -> <4 x i32>. - MVT::ValueType OldVT = N->getValueType(0); - MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT); - assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) && + MVT OldVT = N->getValueType(0); + MVT NewVT = TLI.getTypeToTransformTo(OldVT); + assert(OldVT.getSizeInBits() == 2 * NewVT.getSizeInBits() && "Do not know how to handle this expansion!"); SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT, - MVT::getVectorType(NewVT, 2 * OldElts), + MVT::getVectorVT(NewVT, 2*OldElts), OldVec); // Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector. SDOperand Idx = N->getOperand(1); // Make sure the type of Idx is big enough to hold the new values. - if (MVT::getSizeInBits(Idx.getValueType()) < - MVT::getSizeInBits(TLI.getPointerTy())) + if (Idx.getValueType().getSizeInBits() < TLI.getPointerTy().getSizeInBits()) Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx); @@ -856,10 +856,10 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, SDOperand InL, InH; GetExpandedOp(N->getOperand(0), InL, InH); - MVT::ValueType NVT = InL.getValueType(); - unsigned VTBits = MVT::getSizeInBits(N->getValueType(0)); - unsigned NVTBits = MVT::getSizeInBits(NVT); - MVT::ValueType ShTy = N->getOperand(1).getValueType(); + MVT NVT = InL.getValueType(); + unsigned VTBits = N->getValueType(0).getSizeInBits(); + unsigned NVTBits = NVT.getSizeInBits(); + MVT ShTy = N->getOperand(1).getValueType(); if (N->getOpcode() == ISD::SHL) { if (Amt > VTBits) { @@ -932,10 +932,10 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, bool DAGTypeLegalizer:: ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) { SDOperand Amt = N->getOperand(1); - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - MVT::ValueType ShTy = Amt.getValueType(); - MVT::ValueType ShBits = MVT::getSizeInBits(ShTy); - unsigned NVTBits = MVT::getSizeInBits(NVT); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT ShTy = Amt.getValueType(); + unsigned ShBits = ShTy.getSizeInBits(); + unsigned NVTBits = NVT.getSizeInBits(); assert(isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"); @@ -1077,14 +1077,14 @@ SDOperand DAGTypeLegalizer::ExpandOperand_TRUNCATE(SDNode *N) { } SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) { - if (MVT::isVector(N->getValueType(0))) { + if (N->getValueType(0).isVector()) { // An illegal integer type is being converted to a legal vector type. // Make a two element vector out of the expanded parts and convert that // instead, but only if the new vector type is legal (otherwise there // is no point, and it might create expansion loops). For example, on // x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32. - MVT::ValueType OVT = N->getOperand(0).getValueType(); - MVT::ValueType NVT = MVT::getVectorType(TLI.getTypeToTransformTo(OVT), 2); + MVT OVT = N->getOperand(0).getValueType(); + MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2); if (isTypeLegal(NVT)) { SDOperand Parts[2]; @@ -1103,9 +1103,9 @@ SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) { } SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source, - MVT::ValueType DestTy) { + MVT DestTy) { // We know the destination is legal, but that the input needs to be expanded. - MVT::ValueType SourceVT = Source.getValueType(); + MVT SourceVT = Source.getValueType(); // Check to see if the target has a custom way to lower this. If so, use it. switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { @@ -1149,7 +1149,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source, } SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source, - MVT::ValueType DestTy) { + MVT DestTy) { // We know the destination is legal, but that the input needs to be expanded. assert(getTypeAction(Source.getValueType()) == Expand && "This is not an expansion!"); @@ -1179,7 +1179,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source, SDOperand FudgeInReg; if (DestTy == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); - else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) + else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits()) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), CPIdx, NULL, 0, MVT::f32); @@ -1234,7 +1234,7 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS, GetExpandedOp(NewLHS, LHSLo, LHSHi); GetExpandedOp(NewRHS, RHSLo, RHSHi); - MVT::ValueType VT = NewLHS.getValueType(); + MVT VT = NewLHS.getValueType(); if (VT == MVT::ppcf128) { // FIXME: This generated code sucks. We want to generate // FCMP crN, hi1, hi2 @@ -1343,8 +1343,8 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) { // FIXME: Add support for indexed stores. assert(OpNo == 1 && "Can only expand the stored value so far"); - MVT::ValueType VT = N->getOperand(1).getValueType(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getOperand(1).getValueType(); + MVT NVT = TLI.getTypeToTransformTo(VT); SDOperand Ch = N->getChain(); SDOperand Ptr = N->getBasePtr(); int SVOffset = N->getSrcValueOffset(); @@ -1352,12 +1352,12 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) { bool isVolatile = N->isVolatile(); SDOperand Lo, Hi; - assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!"); + assert(!(NVT.getSizeInBits() & 7) && "Expanded type not byte sized!"); if (!N->isTruncatingStore()) { unsigned IncrementSize = 0; GetExpandedOp(N->getValue(), Lo, Hi); - IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; + IncrementSize = Hi.getValueType().getSizeInBits()/8; if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -1371,7 +1371,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) { Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, isVolatile, MinAlign(Alignment, IncrementSize)); return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); - } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) { + } else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) { GetExpandedOp(N->getValue(), Lo, Hi); return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, N->getMemoryVT(), isVolatile, Alignment); @@ -1383,11 +1383,11 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) { isVolatile, Alignment); unsigned ExcessBits = - MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT); - MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits); + N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); + MVT NEVT = MVT::getIntegerVT(ExcessBits); // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), @@ -1399,17 +1399,16 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) { // the cost of some bit-fiddling. GetExpandedOp(N->getValue(), Lo, Hi); - MVT::ValueType EVT = N->getMemoryVT(); - unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8; - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + MVT EVT = N->getMemoryVT(); + unsigned EBytes = EVT.getStoreSizeInBits()/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; unsigned ExcessBits = (EBytes - IncrementSize)*8; - MVT::ValueType HiVT = - MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits); + MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); - if (ExcessBits < MVT::getSizeInBits(NVT)) { + if (ExcessBits < NVT.getSizeInBits()) { // Transfer high bits from the top of Lo to the bottom of Hi. Hi = DAG.getNode(ISD::SHL, NVT, Hi, - DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits, + DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getShiftAmountTy())); Hi = DAG.getNode(ISD::OR, NVT, Hi, DAG.getNode(ISD::SRL, NVT, Lo, @@ -1427,7 +1426,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) { // Store the lowest ExcessBits bits in the second half. Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset+IncrementSize, - MVT::getIntegerType(ExcessBits), + MVT::getIntegerVT(ExcessBits), isVolatile, MinAlign(Alignment, IncrementSize)); return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); } @@ -1435,12 +1434,12 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) { SDOperand DAGTypeLegalizer::ExpandOperand_BUILD_VECTOR(SDNode *N) { // The vector type is legal but the element type needs expansion. - MVT::ValueType VecVT = N->getValueType(0); - unsigned NumElts = MVT::getVectorNumElements(VecVT); - MVT::ValueType OldVT = N->getOperand(0).getValueType(); - MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT); + MVT VecVT = N->getValueType(0); + unsigned NumElts = VecVT.getVectorNumElements(); + MVT OldVT = N->getOperand(0).getValueType(); + MVT NewVT = TLI.getTypeToTransformTo(OldVT); - assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) && + assert(OldVT.getSizeInBits() == 2 * NewVT.getSizeInBits() && "Do not know how to expand this operand!"); // Build a vector of twice the length out of the expanded elements. @@ -1458,7 +1457,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_BUILD_VECTOR(SDNode *N) { } SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR, - MVT::getVectorType(NewVT, NewElts.size()), + MVT::getVectorVT(NewVT, NewElts.size()), &NewElts[0], NewElts.size()); // Convert the new vector to the old vector type. diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp index f23b63eb1d5..58fcf103889 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp @@ -21,7 +21,7 @@ using namespace llvm; /// GetFPLibCall - Return the right libcall for the given floating point type. -static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, +static RTLIB::Libcall GetFPLibCall(MVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, @@ -105,7 +105,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_ConstantFP(ConstantFPSDNode *N) { } SDOperand DAGTypeLegalizer::FloatToIntRes_FADD(SDNode *N) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)), GetIntegerOp(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -120,11 +120,11 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FCOPYSIGN(SDNode *N) { SDOperand LHS = GetIntegerOp(N->getOperand(0)); SDOperand RHS = BitConvertToInteger(N->getOperand(1)); - MVT::ValueType LVT = LHS.getValueType(); - MVT::ValueType RVT = RHS.getValueType(); + MVT LVT = LHS.getValueType(); + MVT RVT = RHS.getValueType(); - unsigned LSize = MVT::getSizeInBits(LVT); - unsigned RSize = MVT::getSizeInBits(RVT); + unsigned LSize = LVT.getSizeInBits(); + unsigned RSize = RVT.getSizeInBits(); // First get the sign bit of second operand. SDOperand SignBit = DAG.getNode(ISD::SHL, RVT, DAG.getConstant(1, RVT), @@ -133,7 +133,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FCOPYSIGN(SDNode *N) { SignBit = DAG.getNode(ISD::AND, RVT, RHS, SignBit); // Shift right or sign-extend it if the two operands have different types. - int SizeDiff = MVT::getSizeInBits(RVT) - MVT::getSizeInBits(LVT); + int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits(); if (SizeDiff > 0) { SignBit = DAG.getNode(ISD::SRL, RVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); @@ -156,7 +156,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FCOPYSIGN(SDNode *N) { } SDOperand DAGTypeLegalizer::FloatToIntRes_FMUL(SDNode *N) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)), GetIntegerOp(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -168,7 +168,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FMUL(SDNode *N) { } SDOperand DAGTypeLegalizer::FloatToIntRes_FSUB(SDNode *N) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)), GetIntegerOp(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -181,8 +181,8 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_FSUB(SDNode *N) { SDOperand DAGTypeLegalizer::FloatToIntRes_LOAD(SDNode *N) { LoadSDNode *L = cast<LoadSDNode>(N); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); if (L->getExtensionType() == ISD::NON_EXTLOAD) return DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), @@ -202,7 +202,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_LOAD(SDNode *N) { SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) { bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; - MVT::ValueType DestVT = N->getValueType(0); + MVT DestVT = N->getValueType(0); SDOperand Op = N->getOperand(0); if (Op.getValueType() == MVT::i32) { @@ -212,8 +212,9 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) { SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); // word offset constant for Hi/Lo address computation - SDOperand Offset = DAG.getConstant(MVT::getSizeInBits(MVT::i32) / 8, - TLI.getPointerTy()); + SDOperand Offset = + DAG.getConstant(MVT(MVT::i32).getSizeInBits() / 8, + TLI.getPointerTy()); // set up Hi and Lo (into buffer) address based on endian SDOperand Hi = StackSlot; SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, Offset); @@ -251,10 +252,12 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) { if (DestVT == MVT::f64) { // do nothing Result = Sub; - } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { + } else if (DestVT.getSizeInBits() < + MVT(MVT::f64).getSizeInBits()) { Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, DAG.getIntPtrConstant(0)); - } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { + } else if (DestVT.getSizeInBits() > + MVT(MVT::f64).getSizeInBits()) { Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); } return BitConvertToInteger(Result); @@ -273,7 +276,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) { // as a negative number. To counteract this, the dynamic code adds an // offset depending on the data type. uint64_t FF; - switch (Op.getValueType()) { + switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Unsupported integer type!"); case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp index 6d7f0630aed..b0a8475b33b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp @@ -91,7 +91,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_UNDEF(SDNode *N) { } SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // Zero extend things like i1, sign extend everything else. It shouldn't // matter in theory which one we pick, but this tends to give better code? unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; @@ -115,8 +115,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) { break; } - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) && + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() && "Truncation doesn't make sense!"); if (Res.getValueType() == NVT) return Res; @@ -126,11 +126,11 @@ SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) { } SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); if (getTypeAction(N->getOperand(0).getValueType()) == Promote) { SDOperand Res = GetPromotedOp(N->getOperand(0)); - assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) && + assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() && "Extension doesn't make sense!"); // If the result and operand types are the same after promotion, simplify @@ -168,7 +168,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) { Op = GetPromotedOp(Op); unsigned NewOpc = N->getOpcode(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); // If we're promoting a UINT to a larger size, check to see if the new node // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since @@ -194,7 +194,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) { // FIXME: Add support for indexed loads. - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), @@ -218,9 +218,9 @@ SDOperand DAGTypeLegalizer::PromoteResult_BUILD_PAIR(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) { SDOperand InOp = N->getOperand(0); - MVT::ValueType InVT = InOp.getValueType(); - MVT::ValueType NInVT = TLI.getTypeToTransformTo(InVT); - MVT::ValueType OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT InVT = InOp.getValueType(); + MVT NInVT = TLI.getTypeToTransformTo(InVT); + MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); switch (getTypeAction(InVT)) { default: @@ -229,7 +229,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) { case Legal: break; case Promote: - if (MVT::getSizeInBits(OutVT) == MVT::getSizeInBits(NInVT)) + if (OutVT.getSizeInBits() == NInVT.getSizeInBits()) // The input promotes to the same size. Convert the promoted value. return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedOp(InOp)); break; @@ -254,7 +254,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) { std::swap(Lo, Hi); InOp = DAG.getNode(ISD::ANY_EXTEND, - MVT::getIntegerType(MVT::getSizeInBits(OutVT)), + MVT::getIntegerVT(OutVT.getSizeInBits()), JoinIntegers(Lo, Hi)); return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); } @@ -278,7 +278,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) { // Sign extend the input. SDOperand LHS = GetPromotedOp(N->getOperand(0)); SDOperand RHS = GetPromotedOp(N->getOperand(1)); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, DAG.getValueType(VT)); RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, @@ -291,7 +291,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) { // Zero extend the input. SDOperand LHS = GetPromotedOp(N->getOperand(0)); SDOperand RHS = GetPromotedOp(N->getOperand(1)); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); LHS = DAG.getZeroExtendInReg(LHS, VT); RHS = DAG.getZeroExtendInReg(RHS, VT); @@ -305,8 +305,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) { // The input value must be properly sign extended. - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); SDOperand Res = GetPromotedOp(N->getOperand(0)); Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); @@ -314,8 +314,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) { // The input value must be properly zero extended. - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); SDOperand Res = GetPromotedZExtOp(N->getOperand(0)); return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); } @@ -335,41 +335,41 @@ SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteResult_CTLZ(SDNode *N) { SDOperand Op = GetPromotedOp(N->getOperand(0)); - MVT::ValueType OVT = N->getValueType(0); - MVT::ValueType NVT = Op.getValueType(); + MVT OVT = N->getValueType(0); + MVT NVT = Op.getValueType(); // Zero extend to the promoted type and do the count there. Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); // Subtract off the extra leading bits in the bigger type. return DAG.getNode(ISD::SUB, NVT, Op, - DAG.getConstant(MVT::getSizeInBits(NVT) - - MVT::getSizeInBits(OVT), NVT)); + DAG.getConstant(NVT.getSizeInBits() - + OVT.getSizeInBits(), NVT)); } SDOperand DAGTypeLegalizer::PromoteResult_CTPOP(SDNode *N) { SDOperand Op = GetPromotedOp(N->getOperand(0)); - MVT::ValueType OVT = N->getValueType(0); - MVT::ValueType NVT = Op.getValueType(); + MVT OVT = N->getValueType(0); + MVT NVT = Op.getValueType(); // Zero extend to the promoted type and do the count there. return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); } SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) { SDOperand Op = GetPromotedOp(N->getOperand(0)); - MVT::ValueType OVT = N->getValueType(0); - MVT::ValueType NVT = Op.getValueType(); + MVT OVT = N->getValueType(0); + MVT NVT = Op.getValueType(); // The count is the same in the promoted type except if the original // value was zero. This can be handled by setting the bit just off // the top of the original type. Op = DAG.getNode(ISD::OR, NVT, Op, // FIXME: Do this using an APINT constant. - DAG.getConstant(1UL << MVT::getSizeInBits(OVT), NVT)); + DAG.getConstant(1UL << OVT.getSizeInBits(), NVT)); return DAG.getNode(ISD::CTTZ, NVT, Op); } SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) { - MVT::ValueType OldVT = N->getValueType(0); + MVT OldVT = N->getValueType(0); SDOperand OldVec = N->getOperand(0); - unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType()); + unsigned OldElts = OldVec.getValueType().getVectorNumElements(); if (OldElts == 1) { assert(!isTypeLegal(OldVec.getValueType()) && @@ -384,11 +384,11 @@ SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) { // Convert to a vector half as long with an element type of twice the width, // for example <4 x i16> -> <2 x i32>. assert(!(OldElts & 1) && "Odd length vectors not supported!"); - MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT)); - assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT)); + MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); + assert(OldVT.isSimple() && NewVT.isSimple()); SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT, - MVT::getVectorType(NewVT, OldElts / 2), + MVT::getVectorVT(NewVT, OldElts / 2), OldVec); // Extract the element at OldIdx / 2 from the new vector. @@ -401,7 +401,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) { // Hi if it was odd. SDOperand Lo = Elt; SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt, - DAG.getConstant(MVT::getSizeInBits(OldVT), + DAG.getConstant(OldVT.getSizeInBits(), TLI.getShiftAmountTy())); if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -513,7 +513,7 @@ SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) { SDOperand In = GetPromotedOp(N->getOperand(0)); - MVT::ValueType OpVT = N->getOperand(0).getValueType(); + MVT OpVT = N->getOperand(0).getValueType(); if (N->getOpcode() == ISD::UINT_TO_FP) In = DAG.getZeroExtendInReg(In, OpVT); else @@ -525,14 +525,14 @@ SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_PAIR(SDNode *N) { // Since the result type is legal, the operands must promote to it. - MVT::ValueType OVT = N->getOperand(0).getValueType(); + MVT OVT = N->getOperand(0).getValueType(); SDOperand Lo = GetPromotedOp(N->getOperand(0)); SDOperand Hi = GetPromotedOp(N->getOperand(1)); assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); Lo = DAG.getZeroExtendInReg(Lo, OVT); Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, - DAG.getConstant(MVT::getSizeInBits(OVT), + DAG.getConstant(OVT.getSizeInBits(), TLI.getShiftAmountTy())); return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); } @@ -597,14 +597,14 @@ SDOperand DAGTypeLegalizer::PromoteOperand_SETCC(SDNode *N, unsigned OpNo) { /// shared among BR_CC, SELECT_CC, and SETCC handlers. void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS, ISD::CondCode CCCode) { - MVT::ValueType VT = NewLHS.getValueType(); + MVT VT = NewLHS.getValueType(); // Get the promoted values. NewLHS = GetPromotedOp(NewLHS); NewRHS = GetPromotedOp(NewRHS); // If this is an FP compare, the operands have already been extended. - if (!MVT::isInteger(NewLHS.getValueType())) + if (!NewLHS.getValueType().isInteger()) return; // Otherwise, we have to insert explicit sign or zero extends. Note @@ -658,15 +658,15 @@ SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) { // The vector type is legal but the element type is not. This implies // that the vector is a power-of-two in length and that the element // type does not have a strange size (eg: it is not i1). - MVT::ValueType VecVT = N->getValueType(0); - unsigned NumElts = MVT::getVectorNumElements(VecVT); + MVT VecVT = N->getValueType(0); + unsigned NumElts = VecVT.getVectorNumElements(); assert(!(NumElts & 1) && "Legal vector of one illegal element?"); // Build a vector of half the length out of elements of twice the bitwidth. // For example <4 x i16> -> <2 x i32>. - MVT::ValueType OldVT = N->getOperand(0).getValueType(); - MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT)); - assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT)); + MVT OldVT = N->getOperand(0).getValueType(); + MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); + assert(OldVT.isSimple() && NewVT.isSimple()); std::vector<SDOperand> NewElts; NewElts.reserve(NumElts/2); @@ -681,7 +681,7 @@ SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) { } SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR, - MVT::getVectorType(NewVT, NewElts.size()), + MVT::getVectorVT(NewVT, NewElts.size()), &NewElts[0], NewElts.size()); // Convert the new vector to the old vector type. @@ -695,8 +695,8 @@ SDOperand DAGTypeLegalizer::PromoteOperand_INSERT_VECTOR_ELT(SDNode *N, // have to match the vector element type. // Check that any extra bits introduced will be truncated away. - assert(MVT::getSizeInBits(N->getOperand(1).getValueType()) >= - MVT::getSizeInBits(MVT::getVectorElementType(N->getValueType(0))) && + assert(N->getOperand(1).getValueType().getSizeInBits() >= + N->getValueType(0).getVectorElementType().getSizeInBits() && "Type of inserted value narrower than vector element type!"); return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), GetPromotedOp(N->getOperand(1)), diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp index d9ba99fb896..eaab770088e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp @@ -89,12 +89,12 @@ void DAGTypeLegalizer::ScalarizeResult(SDNode *N, unsigned ResNo) { } SDOperand DAGTypeLegalizer::ScalarizeRes_UNDEF(SDNode *N) { - return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(N->getValueType(0))); + return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType()); } SDOperand DAGTypeLegalizer::ScalarizeRes_LOAD(LoadSDNode *N) { // FIXME: Add support for indexed loads. - SDOperand Result = DAG.getLoad(MVT::getVectorElementType(N->getValueType(0)), + SDOperand Result = DAG.getLoad(N->getValueType(0).getVectorElementType(), N->getChain(), N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), N->isVolatile(), N->getAlignment()); @@ -125,8 +125,8 @@ SDOperand DAGTypeLegalizer::ScalarizeRes_INSERT_VECTOR_ELT(SDNode *N) { // The value to insert may have a wider type than the vector element type, // so be sure to truncate it to the element type if necessary. SDOperand Op = N->getOperand(1); - MVT::ValueType EltVT = MVT::getVectorElementType(N->getValueType(0)); - if (MVT::getSizeInBits(Op.getValueType()) > MVT::getSizeInBits(EltVT)) + MVT EltVT = N->getValueType(0).getVectorElementType(); + if (Op.getValueType().getSizeInBits() > EltVT.getSizeInBits()) Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op); assert(Op.getValueType() == EltVT && "Invalid type for inserted value!"); return Op; @@ -140,7 +140,7 @@ SDOperand DAGTypeLegalizer::ScalarizeRes_VECTOR_SHUFFLE(SDNode *N) { } SDOperand DAGTypeLegalizer::ScalarizeRes_BIT_CONVERT(SDNode *N) { - MVT::ValueType NewVT = MVT::getVectorElementType(N->getValueType(0)); + MVT NewVT = N->getValueType(0).getVectorElementType(); return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0)); } diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp index d1057c98cd0..a7c64862a33 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp @@ -19,18 +19,17 @@ using namespace llvm; /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a vector /// type that needs to be split. This handles non-power of two vectors. -static void GetSplitDestVTs(MVT::ValueType InVT, - MVT::ValueType &Lo, MVT::ValueType &Hi) { - MVT::ValueType NewEltVT = MVT::getVectorElementType(InVT); - unsigned NumElements = MVT::getVectorNumElements(InVT); +static void GetSplitDestVTs(MVT InVT, MVT &Lo, MVT &Hi) { + MVT NewEltVT = InVT.getVectorElementType(); + unsigned NumElements = InVT.getVectorNumElements(); if ((NumElements & (NumElements-1)) == 0) { // Simple power of two vector. NumElements >>= 1; - Lo = Hi = MVT::getVectorType(NewEltVT, NumElements); + Lo = Hi = MVT::getVectorVT(NewEltVT, NumElements); } else { // Non-power-of-two vectors. unsigned NewNumElts_Lo = 1 << Log2_32(NumElements); unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; - Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); - Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); + Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); + Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); } } @@ -117,7 +116,7 @@ void DAGTypeLegalizer::SplitResult(SDNode *N, unsigned ResNo) { } void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); Lo = DAG.getNode(ISD::UNDEF, LoVT); @@ -127,7 +126,7 @@ void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) { void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD, SDOperand &Lo, SDOperand &Hi) { // FIXME: Add support for indexed loads. - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); SDOperand Ch = LD->getChain(); @@ -138,7 +137,7 @@ void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD, bool isVolatile = LD->isVolatile(); Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); - unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8; + unsigned IncrementSize = LoVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); SVOffset += IncrementSize; @@ -166,7 +165,7 @@ void DAGTypeLegalizer::SplitRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, GetSplitOp(N->getOperand(0), Lo, Hi); unsigned Index = cast<ConstantSDNode>(N->getOperand(2))->getValue(); SDOperand ScalarOp = N->getOperand(1); - unsigned LoNumElts = MVT::getVectorNumElements(Lo.getValueType()); + unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); if (Index < LoNumElts) Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, ScalarOp, N->getOperand(2)); @@ -180,10 +179,10 @@ void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N, // Build the low part. SDOperand Mask = N->getOperand(2); SmallVector<SDOperand, 16> Ops; - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); - MVT::ValueType EltVT = MVT::getVectorElementType(LoVT); - unsigned LoNumElts = MVT::getVectorNumElements(LoVT); + MVT EltVT = LoVT.getVectorElementType(); + unsigned LoNumElts = LoVT.getVectorNumElements(); unsigned NumElements = Mask.getNumOperands(); // Insert all of the elements from the input that are needed. We use @@ -217,9 +216,9 @@ void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N, void DAGTypeLegalizer::SplitRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); - unsigned LoNumElts = MVT::getVectorNumElements(LoVT); + unsigned LoNumElts = LoVT.getVectorNumElements(); SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size()); @@ -237,7 +236,7 @@ void DAGTypeLegalizer::SplitRes_CONCAT_VECTORS(SDNode *N, return; } - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); @@ -251,11 +250,11 @@ void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // We know the result is a vector. The input may be either a vector or a // scalar value. - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); SDOperand InOp = N->getOperand(0); - MVT::ValueType InVT = InOp.getValueType(); + MVT InVT = InOp.getValueType(); // Handle some special cases efficiently. switch (getTypeAction(InVT)) { @@ -289,8 +288,8 @@ void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N, } // In the general case, convert the input to an integer and split it by hand. - MVT::ValueType LoIntVT = MVT::getIntegerType(MVT::getSizeInBits(LoVT)); - MVT::ValueType HiIntVT = MVT::getIntegerType(MVT::getSizeInBits(HiVT)); + MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits()); + MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits()); if (TLI.isBigEndian()) std::swap(LoIntVT, HiIntVT); @@ -314,7 +313,7 @@ void DAGTypeLegalizer::SplitRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) { void DAGTypeLegalizer::SplitRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // Get the dest types. This doesn't always match input types, e.g. int_to_fp. - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); GetSplitOp(N->getOperand(0), Lo, Hi); @@ -410,7 +409,7 @@ SDOperand DAGTypeLegalizer::SplitOp_STORE(StoreSDNode *N, unsigned OpNo) { SDOperand Lo, Hi; GetSplitOp(N->getOperand(1), Lo, Hi); - unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; + unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment); @@ -455,17 +454,16 @@ SDOperand DAGTypeLegalizer::SplitOp_BIT_CONVERT(SDNode *N) { SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) { SDOperand Vec = N->getOperand(0); SDOperand Idx = N->getOperand(1); - MVT::ValueType VecVT = Vec.getValueType(); + MVT VecVT = Vec.getValueType(); if (isa<ConstantSDNode>(Idx)) { uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue(); - assert(IdxVal < MVT::getVectorNumElements(VecVT) && - "Invalid vector index!"); + assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); SDOperand Lo, Hi; GetSplitOp(Vec, Lo, Hi); - uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType()); + uint64_t LoElts = Lo.getValueType().getVectorNumElements(); if (IdxVal < LoElts) return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx); @@ -480,13 +478,12 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) { SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); // Add the offset to the index. - MVT::ValueType EltVT = MVT::getVectorElementType(VecVT); - unsigned EltSize = MVT::getSizeInBits(EltVT)/8; // FIXME: should be ABI size. + MVT EltVT = VecVT.getVectorElementType(); + unsigned EltSize = EltVT.getSizeInBits()/8; // FIXME: should be ABI size. Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, DAG.getConstant(EltSize, Idx.getValueType())); - if (MVT::getSizeInBits(Idx.getValueType()) > - MVT::getSizeInBits(TLI.getPointerTy())) + if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits()) Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); else Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); @@ -498,16 +495,16 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) { SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) { // We know that the extracted result type is legal. For now, assume the index // is a constant. - MVT::ValueType SubVT = N->getValueType(0); + MVT SubVT = N->getValueType(0); SDOperand Idx = N->getOperand(1); SDOperand Lo, Hi; GetSplitOp(N->getOperand(0), Lo, Hi); - uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType()); + uint64_t LoElts = Lo.getValueType().getVectorNumElements(); uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue(); if (IdxVal < LoElts) { - assert(IdxVal + MVT::getVectorNumElements(SubVT) <= LoElts && + assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && "Extracted subvector crosses vector split!"); return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx); } else { @@ -519,7 +516,7 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) { SDOperand DAGTypeLegalizer::SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) { assert(OpNo == 2 && "Shuffle source type differs from result type?"); SDOperand Mask = N->getOperand(2); - unsigned MaskLength = MVT::getVectorNumElements(Mask.getValueType()); + unsigned MaskLength = Mask.getValueType().getVectorNumElements(); unsigned LargestMaskEntryPlusOne = 2 * MaskLength; unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne); @@ -532,12 +529,12 @@ SDOperand DAGTypeLegalizer::SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) { EltVT = MVT::SimpleValueType(EltVT + 1)) { // Is the element type big enough to hold the values? - if (MVT::getSizeInBits(EltVT) < MinimumBitWidth) + if (MVT(EltVT).getSizeInBits() < MinimumBitWidth) // Nope. continue; // Is the vector type legal? - MVT::ValueType VecVT = MVT::getVectorType(EltVT, MaskLength); + MVT VecVT = MVT::getVectorVT(EltVT, MaskLength); if (!isTypeLegal(VecVT)) // Nope. continue; diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 70365e2babf..d60d2b02ef0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -191,7 +191,7 @@ void ScheduleDAG::BuildSchedUnits() { assert(OpSU && "Node has no SUnit!"); if (OpSU == SU) continue; // In the same group. - MVT::ValueType OpVT = N->getOperand(i).getValueType(); + MVT OpVT = N->getOperand(i).getValueType(); assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); bool isChain = OpVT == MVT::Other; @@ -433,7 +433,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, SDOperand Op = Use->getOperand(i); if (Op.Val != Node || Op.ResNo != ResNo) continue; - MVT::ValueType VT = Node->getValueType(Op.ResNo); + MVT VT = Node->getValueType(Op.ResNo); if (VT != MVT::Other && VT != MVT::Flag) Match = false; } @@ -677,7 +677,7 @@ static const TargetRegisterClass *getSubRegisterRegClass( static const TargetRegisterClass *getSuperregRegisterClass( const TargetRegisterClass *TRC, unsigned SubIdx, - MVT::ValueType VT) { + MVT VT) { // Pick the register class of the superegister for this type for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), E = TRC->superregclasses_end(); I != E; ++I) diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index f84b3f05577..d2ed4eff44d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -646,7 +646,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { SUnit *NewSU; bool TryUnfold = false; for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { - MVT::ValueType VT = N->getValueType(i); + MVT VT = N->getValueType(i); if (VT == MVT::Flag) return NULL; else if (VT == MVT::Other) @@ -654,7 +654,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { } for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { const SDOperand &Op = N->getOperand(i); - MVT::ValueType VT = Op.Val->getValueType(Op.ResNo); + MVT VT = Op.Val->getValueType(Op.ResNo); if (VT == MVT::Flag) return NULL; } @@ -872,8 +872,8 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, /// getPhysicalRegisterVT - Returns the ValueType of the physical register /// definition of the specified node. /// FIXME: Move to SelectionDAG? -static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg, - const TargetInstrInfo *TII) { +static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, + const TargetInstrInfo *TII) { const TargetInstrDesc &TID = TII->get(N->getTargetOpcode()); assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); unsigned NumRes = TID.getNumDefs(); @@ -1022,7 +1022,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { SUnit *NewDef = CopyAndMoveSuccessors(LRDef); if (!NewDef) { // Issue expensive cross register class copies. - MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); + MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); const TargetRegisterClass *RC = TRI->getPhysicalRegisterRegClass(Reg, VT); const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); @@ -1599,7 +1599,7 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, if (!SUImpDefs) return false; for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { - MVT::ValueType VT = N->getValueType(i); + MVT VT = N->getValueType(i); if (VT == MVT::Flag || VT == MVT::Other) continue; unsigned Reg = ImpDefs[i - NumDefs]; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 8d0d344d62b..db73ab4650d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -40,13 +40,13 @@ using namespace llvm; /// makeVTList - Return an instance of the SDVTList struct initialized with the /// specified members. -static SDVTList makeVTList(const MVT::ValueType *VTs, unsigned NumVTs) { +static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { SDVTList Res = {VTs, NumVTs}; return Res; } -static const fltSemantics *MVTToAPFloatSemantics(MVT::ValueType VT) { - switch (VT) { +static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { + switch (VT.getSimpleVT()) { default: assert(0 && "Unknown FP format"); case MVT::f32: return &APFloat::IEEEsingle; case MVT::f64: return &APFloat::IEEEdouble; @@ -70,9 +70,9 @@ bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { return Value.bitwiseIsEqual(V); } -bool ConstantFPSDNode::isValueValidForType(MVT::ValueType VT, +bool ConstantFPSDNode::isValueValidForType(MVT VT, const APFloat& Val) { - assert(MVT::isFloatingPoint(VT) && "Can only convert between FP types"); + assert(VT.isFloatingPoint() && "Can only convert between FP types"); // PPC long double cannot be converted to any other type. if (VT == MVT::ppcf128 || @@ -416,7 +416,7 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) { LoadSDNode *LD = cast<LoadSDNode>(N); ID.AddInteger(LD->getAddressingMode()); ID.AddInteger(LD->getExtensionType()); - ID.AddInteger((unsigned int)(LD->getMemoryVT())); + ID.AddInteger(LD->getMemoryVT().V); ID.AddInteger(LD->getAlignment()); ID.AddInteger(LD->isVolatile()); break; @@ -425,7 +425,7 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) { StoreSDNode *ST = cast<StoreSDNode>(N); ID.AddInteger(ST->getAddressingMode()); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger((unsigned int)(ST->getMemoryVT())); + ID.AddInteger(ST->getMemoryVT().V); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); break; @@ -574,12 +574,12 @@ void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); break; case ISD::VALUETYPE: { - MVT::ValueType VT = cast<VTSDNode>(N)->getVT(); - if (MVT::isExtendedVT(VT)) { + MVT VT = cast<VTSDNode>(N)->getVT(); + if (VT.isExtended()) { Erased = ExtendedValueTypeNodes.erase(VT); } else { - Erased = ValueTypeNodes[VT] != 0; - ValueTypeNodes[VT] = 0; + Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; + ValueTypeNodes[VT.getSimpleVT()] = 0; } break; } @@ -684,13 +684,13 @@ SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { ID.AddInteger(LD->getAddressingMode()); ID.AddInteger(LD->getExtensionType()); - ID.AddInteger((unsigned int)(LD->getMemoryVT())); + ID.AddInteger(LD->getMemoryVT().V); ID.AddInteger(LD->getAlignment()); ID.AddInteger(LD->isVolatile()); } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { ID.AddInteger(ST->getAddressingMode()); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger((unsigned int)(ST->getMemoryVT())); + ID.AddInteger(ST->getMemoryVT().V); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); } @@ -712,10 +712,10 @@ SelectionDAG::~SelectionDAG() { } } -SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { +SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT VT) { if (Op.getValueType() == VT) return Op; APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), - MVT::getSizeInBits(VT)); + VT.getSizeInBits()); return getNode(ISD::AND, Op.getValueType(), Op, getConstant(Imm, Op.getValueType())); } @@ -729,20 +729,20 @@ SDOperand SelectionDAG::getString(const std::string &Val) { return SDOperand(N, 0); } -SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT, bool isT) { - MVT::ValueType EltVT = - MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; +SDOperand SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { + MVT EltVT = + VT.isVector() ? VT.getVectorElementType() : VT; - return getConstant(APInt(MVT::getSizeInBits(EltVT), Val), VT, isT); + return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); } -SDOperand SelectionDAG::getConstant(const APInt &Val, MVT::ValueType VT, bool isT) { - assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); +SDOperand SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { + assert(VT.isInteger() && "Cannot create FP integer constant!"); - MVT::ValueType EltVT = - MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; + MVT EltVT = + VT.isVector() ? VT.getVectorElementType() : VT; - assert(Val.getBitWidth() == MVT::getSizeInBits(EltVT) && + assert(Val.getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"); unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; @@ -752,7 +752,7 @@ SDOperand SelectionDAG::getConstant(const APInt &Val, MVT::ValueType VT, bool is void *IP = 0; SDNode *N = NULL; if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) - if (!MVT::isVector(VT)) + if (!VT.isVector()) return SDOperand(N, 0); if (!N) { N = new ConstantSDNode(isT, Val, EltVT); @@ -761,9 +761,9 @@ SDOperand SelectionDAG::getConstant(const APInt &Val, MVT::ValueType VT, bool is } SDOperand Result(N, 0); - if (MVT::isVector(VT)) { + if (VT.isVector()) { SmallVector<SDOperand, 8> Ops; - Ops.assign(MVT::getVectorNumElements(VT), Result); + Ops.assign(VT.getVectorNumElements(), Result); Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } return Result; @@ -774,12 +774,11 @@ SDOperand SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { } -SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT, - bool isTarget) { - assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); +SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { + assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); - MVT::ValueType EltVT = - MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; + MVT EltVT = + VT.isVector() ? VT.getVectorElementType() : VT; // Do the map lookup using the actual bit pattern for the floating point // value, so that we don't have problems with 0.0 comparing equal to -0.0, and @@ -791,7 +790,7 @@ SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT, void *IP = 0; SDNode *N = NULL; if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) - if (!MVT::isVector(VT)) + if (!VT.isVector()) return SDOperand(N, 0); if (!N) { N = new ConstantFPSDNode(isTarget, V, EltVT); @@ -800,18 +799,17 @@ SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT, } SDOperand Result(N, 0); - if (MVT::isVector(VT)) { + if (VT.isVector()) { SmallVector<SDOperand, 8> Ops; - Ops.assign(MVT::getVectorNumElements(VT), Result); + Ops.assign(VT.getVectorNumElements(), Result); Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } return Result; } -SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT, - bool isTarget) { - MVT::ValueType EltVT = - MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; +SDOperand SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { + MVT EltVT = + VT.isVector() ? VT.getVectorElementType() : VT; if (EltVT==MVT::f32) return getConstantFP(APFloat((float)Val), VT, isTarget); else @@ -819,7 +817,7 @@ SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT, } SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, - MVT::ValueType VT, int Offset, + MVT VT, int Offset, bool isTargetGA) { unsigned Opc; @@ -848,8 +846,7 @@ SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, return SDOperand(N, 0); } -SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT, - bool isTarget) { +SDOperand SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(VT), (SDOperand*)0, 0); @@ -863,7 +860,7 @@ SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT, return SDOperand(N, 0); } -SDOperand SelectionDAG::getJumpTable(int JTI, MVT::ValueType VT, bool isTarget){ +SDOperand SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(VT), (SDOperand*)0, 0); @@ -877,7 +874,7 @@ SDOperand SelectionDAG::getJumpTable(int JTI, MVT::ValueType VT, bool isTarget){ return SDOperand(N, 0); } -SDOperand SelectionDAG::getConstantPool(Constant *C, MVT::ValueType VT, +SDOperand SelectionDAG::getConstantPool(Constant *C, MVT VT, unsigned Alignment, int Offset, bool isTarget) { unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; @@ -896,8 +893,7 @@ SDOperand SelectionDAG::getConstantPool(Constant *C, MVT::ValueType VT, } -SDOperand SelectionDAG::getConstantPool(MachineConstantPoolValue *C, - MVT::ValueType VT, +SDOperand SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, unsigned Alignment, int Offset, bool isTarget) { unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; @@ -942,12 +938,12 @@ SDOperand SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { return SDOperand(N, 0); } -SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { - if (!MVT::isExtendedVT(VT) && (unsigned)VT >= ValueTypeNodes.size()) - ValueTypeNodes.resize(VT+1); +SDOperand SelectionDAG::getValueType(MVT VT) { + if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) + ValueTypeNodes.resize(VT.getSimpleVT()+1); - SDNode *&N = MVT::isExtendedVT(VT) ? - ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT]; + SDNode *&N = VT.isExtended() ? + ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; if (N) return SDOperand(N, 0); N = new VTSDNode(VT); @@ -955,7 +951,7 @@ SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { return SDOperand(N, 0); } -SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { +SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { SDNode *&N = ExternalSymbols[Sym]; if (N) return SDOperand(N, 0); N = new ExternalSymbolSDNode(false, Sym, VT); @@ -963,8 +959,7 @@ SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { return SDOperand(N, 0); } -SDOperand SelectionDAG::getTargetExternalSymbol(const char *Sym, - MVT::ValueType VT) { +SDOperand SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { SDNode *&N = TargetExternalSymbols[Sym]; if (N) return SDOperand(N, 0); N = new ExternalSymbolSDNode(true, Sym, VT); @@ -975,7 +970,7 @@ SDOperand SelectionDAG::getTargetExternalSymbol(const char *Sym, SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { if ((unsigned)Cond >= CondCodeNodes.size()) CondCodeNodes.resize(Cond+1); - + if (CondCodeNodes[Cond] == 0) { CondCodeNodes[Cond] = new CondCodeSDNode(Cond); AllNodes.push_back(CondCodeNodes[Cond]); @@ -983,7 +978,7 @@ SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { return SDOperand(CondCodeNodes[Cond], 0); } -SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) { +SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT VT) { FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::Register, getVTList(VT), (SDOperand*)0, 0); ID.AddInteger(RegNo); @@ -1039,17 +1034,17 @@ SDOperand SelectionDAG::getMemOperand(const MachineMemOperand &MO) { /// CreateStackTemporary - Create a stack temporary, suitable for holding the /// specified value type. -SDOperand SelectionDAG::CreateStackTemporary(MVT::ValueType VT) { +SDOperand SelectionDAG::CreateStackTemporary(MVT VT) { MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); - unsigned ByteSize = MVT::getSizeInBits(VT)/8; - const Type *Ty = MVT::getTypeForValueType(VT); + unsigned ByteSize = VT.getSizeInBits()/8; + const Type *Ty = VT.getTypeForMVT(); unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); return getFrameIndex(FrameIdx, TLI.getPointerTy()); } -SDOperand SelectionDAG::FoldSetCC(MVT::ValueType VT, SDOperand N1, +SDOperand SelectionDAG::FoldSetCC(MVT VT, SDOperand N1, SDOperand N2, ISD::CondCode Cond) { // These setcc operations always fold. switch (Cond) { @@ -1069,7 +1064,7 @@ SDOperand SelectionDAG::FoldSetCC(MVT::ValueType VT, SDOperand N1, case ISD::SETUO: case ISD::SETUEQ: case ISD::SETUNE: - assert(!MVT::isInteger(N1.getValueType()) && "Illegal setcc for integer!"); + assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); break; } @@ -1177,7 +1172,7 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, unsigned Depth) const { unsigned BitWidth = Mask.getBitWidth(); - assert(BitWidth == MVT::getSizeInBits(Op.getValueType()) && + assert(BitWidth == Op.getValueType().getSizeInBits() && "Mask size mismatches value type size!"); KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. @@ -1372,8 +1367,8 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, } return; case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); - unsigned EBits = MVT::getSizeInBits(EVT); + MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + unsigned EBits = EVT.getSizeInBits(); // Sign extension. Compute the demanded bits in the result that are not // present in the input. @@ -1417,15 +1412,15 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, case ISD::LOAD: { if (ISD::isZEXTLoad(Op.Val)) { LoadSDNode *LD = cast<LoadSDNode>(Op); - MVT::ValueType VT = LD->getMemoryVT(); - unsigned MemBits = MVT::getSizeInBits(VT); + MVT VT = LD->getMemoryVT(); + unsigned MemBits = VT.getSizeInBits(); KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; } return; } case ISD::ZERO_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; APInt InMask = Mask; InMask.trunc(InBits); @@ -1438,8 +1433,8 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, return; } case ISD::SIGN_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt InSignBit = APInt::getSignBit(InBits); APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; APInt InMask = Mask; @@ -1479,8 +1474,8 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, return; } case ISD::ANY_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt InMask = Mask; InMask.trunc(InBits); KnownZero.trunc(InBits); @@ -1491,8 +1486,8 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, return; } case ISD::TRUNCATE: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt InMask = Mask; InMask.zext(InBits); KnownZero.zext(InBits); @@ -1504,8 +1499,8 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, break; } case ISD::AssertZext: { - MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); - APInt InMask = APInt::getLowBitsSet(BitWidth, MVT::getSizeInBits(VT)); + MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, KnownOne, Depth+1); KnownZero |= (~InMask) & Mask; @@ -1624,9 +1619,9 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask, /// information. For example, immediately after an "SRA X, 2", we know that /// the top 3 bits are all equal to each other, so we return 3. unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ - MVT::ValueType VT = Op.getValueType(); - assert(MVT::isInteger(VT) && "Invalid VT!"); - unsigned VTBits = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + assert(VT.isInteger() && "Invalid VT!"); + unsigned VTBits = VT.getSizeInBits(); unsigned Tmp, Tmp2; unsigned FirstAnswer = 1; @@ -1636,10 +1631,10 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ switch (Op.getOpcode()) { default: break; case ISD::AssertSext: - Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); + Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); return VTBits-Tmp+1; case ISD::AssertZext: - Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); + Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); return VTBits-Tmp; case ISD::Constant: { @@ -1653,12 +1648,12 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ } case ISD::SIGN_EXTEND: - Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType()); + Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; case ISD::SIGN_EXTEND_INREG: // Max of the input and what this extends. - Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); + Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); Tmp = VTBits-Tmp+1; Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); @@ -1793,10 +1788,10 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ switch (ExtType) { default: break; case ISD::SEXTLOAD: // '17' bits known - Tmp = MVT::getSizeInBits(LD->getMemoryVT()); + Tmp = LD->getMemoryVT().getSizeInBits(); return VTBits-Tmp+1; case ISD::ZEXTLOAD: // '16' bits known - Tmp = MVT::getSizeInBits(LD->getMemoryVT()); + Tmp = LD->getMemoryVT().getSizeInBits(); return VTBits-Tmp; } } @@ -1848,7 +1843,7 @@ bool SelectionDAG::isVerifiedDebugInfoDesc(SDOperand Op) const { /// getShuffleScalarElt - Returns the scalar element that will make up the ith /// element of the result of the vector shuffle. SDOperand SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned Idx) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); SDOperand PermMask = N->getOperand(2); unsigned NumElems = PermMask.getNumOperands(); SDOperand V = (Idx < NumElems) ? N->getOperand(0) : N->getOperand(1); @@ -1856,18 +1851,18 @@ SDOperand SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned Idx) { if (V.getOpcode() == ISD::BIT_CONVERT) { V = V.getOperand(0); - if (MVT::getVectorNumElements(V.getValueType()) != NumElems) + if (V.getValueType().getVectorNumElements() != NumElems) return SDOperand(); } if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) return (Idx == 0) ? V.getOperand(0) - : getNode(ISD::UNDEF, MVT::getVectorElementType(VT)); + : getNode(ISD::UNDEF, VT.getVectorElementType()); if (V.getOpcode() == ISD::BUILD_VECTOR) return V.getOperand(Idx); if (V.getOpcode() == ISD::VECTOR_SHUFFLE) { SDOperand Elt = PermMask.getOperand(Idx); if (Elt.getOpcode() == ISD::UNDEF) - return getNode(ISD::UNDEF, MVT::getVectorElementType(VT)); + return getNode(ISD::UNDEF, VT.getVectorElementType()); return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Elt)->getValue()); } return SDOperand(); @@ -1876,7 +1871,7 @@ SDOperand SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned Idx) { /// getNode - Gets or creates the specified node. /// -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, getVTList(VT), (SDOperand*)0, 0); void *IP = 0; @@ -1889,12 +1884,11 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { return SDOperand(N, 0); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, - SDOperand Operand) { +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) { // Constant fold unary operations with an integer constant operand. if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { const APInt &Val = C->getAPIntValue(); - unsigned BitWidth = MVT::getSizeInBits(VT); + unsigned BitWidth = VT.getSizeInBits(); switch (Opcode) { default: break; case ISD::SIGN_EXTEND: @@ -1979,56 +1973,56 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, return Operand; // Factor or merge of one node? No need. case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); case ISD::FP_EXTEND: - assert(MVT::isFloatingPoint(VT) && - MVT::isFloatingPoint(Operand.getValueType()) && "Invalid FP cast!"); + assert(VT.isFloatingPoint() && + Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); if (Operand.getValueType() == VT) return Operand; // noop conversion. if (Operand.getOpcode() == ISD::UNDEF) return getNode(ISD::UNDEF, VT); break; case ISD::SIGN_EXTEND: - assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) && + assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid SIGN_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(MVT::getSizeInBits(Operand.getValueType()) < MVT::getSizeInBits(VT) + assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() && "Invalid sext node, dst < src!"); if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); break; case ISD::ZERO_EXTEND: - assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) && + assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ZERO_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(MVT::getSizeInBits(Operand.getValueType()) < MVT::getSizeInBits(VT) + assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() && "Invalid zext node, dst < src!"); if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); break; case ISD::ANY_EXTEND: - assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) && + assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ANY_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(MVT::getSizeInBits(Operand.getValueType()) < MVT::getSizeInBits(VT) + assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() && "Invalid anyext node, dst < src!"); if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); break; case ISD::TRUNCATE: - assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) && + assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid TRUNCATE!"); if (Operand.getValueType() == VT) return Operand; // noop truncate - assert(MVT::getSizeInBits(Operand.getValueType()) > MVT::getSizeInBits(VT) + assert(Operand.getValueType().getSizeInBits() > VT.getSizeInBits() && "Invalid truncate node, src < dst!"); if (OpOpcode == ISD::TRUNCATE) return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ANY_EXTEND) { // If the source is smaller than the dest, we still need an extend. - if (MVT::getSizeInBits(Operand.Val->getOperand(0).getValueType()) - < MVT::getSizeInBits(VT)) + if (Operand.Val->getOperand(0).getValueType().getSizeInBits() + < VT.getSizeInBits()) return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); - else if (MVT::getSizeInBits(Operand.Val->getOperand(0).getValueType()) - > MVT::getSizeInBits(VT)) + else if (Operand.Val->getOperand(0).getValueType().getSizeInBits() + > VT.getSizeInBits()) return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); else return Operand.Val->getOperand(0); @@ -2036,7 +2030,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, break; case ISD::BIT_CONVERT: // Basic sanity checking. - assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType()) + assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Cannot BIT_CONVERT between types of different sizes!"); if (VT == Operand.getValueType()) return Operand; // noop conversion. if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) @@ -2045,8 +2039,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, return getNode(ISD::UNDEF, VT); break; case ISD::SCALAR_TO_VECTOR: - assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) && - MVT::getVectorElementType(VT) == Operand.getValueType() && + assert(VT.isVector() && !Operand.getValueType().isVector() && + VT.getVectorElementType() == Operand.getValueType() && "Illegal SCALAR_TO_VECTOR node!"); if (OpOpcode == ISD::UNDEF) return getNode(ISD::UNDEF, VT); @@ -2090,7 +2084,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2) { ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); @@ -2104,7 +2098,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, if (N2.getOpcode() == ISD::EntryToken) return N1; break; case ISD::AND: - assert(MVT::isInteger(VT) && N1.getValueType() == N2.getValueType() && + assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"); // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's // worth handling here. @@ -2117,7 +2111,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, case ISD::XOR: case ISD::ADD: case ISD::SUB: - assert(MVT::isInteger(VT) && N1.getValueType() == N2.getValueType() && + assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"); // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so // it's worth handling here. @@ -2128,7 +2122,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, case ISD::UREM: case ISD::MULHU: case ISD::MULHS: - assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); + assert(VT.isInteger() && "This operator does not apply to FP types!"); // fall through case ISD::MUL: case ISD::SDIV: @@ -2143,8 +2137,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, break; case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. assert(N1.getValueType() == VT && - MVT::isFloatingPoint(N1.getValueType()) && - MVT::isFloatingPoint(N2.getValueType()) && + N1.getValueType().isFloatingPoint() && + N2.getValueType().isFloatingPoint() && "Invalid FCOPYSIGN!"); break; case ISD::SHL: @@ -2154,49 +2148,49 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, case ISD::ROTR: assert(VT == N1.getValueType() && "Shift operators return type must be the same as their first arg"); - assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && + assert(VT.isInteger() && N2.getValueType().isInteger() && VT != MVT::i1 && "Shifts only work on integers"); break; case ISD::FP_ROUND_INREG: { - MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); + MVT EVT = cast<VTSDNode>(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg round!"); - assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && + assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && "Cannot FP_ROUND_INREG integer types"); - assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) && + assert(EVT.getSizeInBits() <= VT.getSizeInBits() && "Not rounding down!"); if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. break; } case ISD::FP_ROUND: - assert(MVT::isFloatingPoint(VT) && - MVT::isFloatingPoint(N1.getValueType()) && - MVT::getSizeInBits(VT) <= MVT::getSizeInBits(N1.getValueType()) && + assert(VT.isFloatingPoint() && + N1.getValueType().isFloatingPoint() && + VT.getSizeInBits() <= N1.getValueType().getSizeInBits() && isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); if (N1.getValueType() == VT) return N1; // noop conversion. break; case ISD::AssertSext: case ISD::AssertZext: { - MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); + MVT EVT = cast<VTSDNode>(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg extend!"); - assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && + assert(VT.isInteger() && EVT.isInteger() && "Cannot *_EXTEND_INREG FP types"); - assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) && + assert(EVT.getSizeInBits() <= VT.getSizeInBits() && "Not extending!"); if (VT == EVT) return N1; // noop assertion. break; } case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); + MVT EVT = cast<VTSDNode>(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg extend!"); - assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && + assert(VT.isInteger() && EVT.isInteger() && "Cannot *_EXTEND_INREG FP types"); - assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) && + assert(EVT.getSizeInBits() <= VT.getSizeInBits() && "Not extending!"); if (EVT == VT) return N1; // Not actually extending if (N1C) { APInt Val = N1C->getAPIntValue(); - unsigned FromBits = MVT::getSizeInBits(cast<VTSDNode>(N2)->getVT()); + unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); Val <<= Val.getBitWidth()-FromBits; Val = Val.ashr(Val.getBitWidth()-FromBits); return getConstant(Val, VT); @@ -2215,7 +2209,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, if (N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0) { unsigned Factor = - MVT::getVectorNumElements(N1.getOperand(0).getValueType()); + N1.getOperand(0).getValueType().getVectorNumElements(); return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(N2C->getValue() / Factor), getConstant(N2C->getValue() % Factor, N2.getValueType())); @@ -2238,9 +2232,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, break; case ISD::EXTRACT_ELEMENT: assert(N2C && (unsigned)N2C->getValue() < 2 && "Bad EXTRACT_ELEMENT!"); - assert(!MVT::isVector(N1.getValueType()) && - MVT::isInteger(N1.getValueType()) && - !MVT::isVector(VT) && MVT::isInteger(VT) && + assert(!N1.getValueType().isVector() && + N1.getValueType().isInteger() && + !VT.isVector() && VT.isInteger() && "EXTRACT_ELEMENT only applies to integers!"); // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding @@ -2251,7 +2245,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, // EXTRACT_ELEMENT of a constant int is also very common. if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { - unsigned ElementSize = MVT::getSizeInBits(VT); + unsigned ElementSize = VT.getSizeInBits(); unsigned Shift = ElementSize * N2C->getValue(); APInt ShiftedVal = C->getAPIntValue().lshr(Shift); return getConstant(ShiftedVal.trunc(ElementSize), VT); @@ -2365,7 +2359,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, case ISD::SREM: case ISD::SRL: case ISD::SHL: - if (!MVT::isVector(VT)) + if (!VT.isVector()) return getConstant(0, VT); // fold op(undef, arg2) -> 0 // For vectors, we can't easily build an all zero vector, just return // the LHS. @@ -2401,14 +2395,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, case ISD::AND: case ISD::SRL: case ISD::SHL: - if (!MVT::isVector(VT)) + if (!VT.isVector()) return getConstant(0, VT); // fold op(arg1, undef) -> 0 // For vectors, we can't easily build an all zero vector, just return // the LHS. return N1; case ISD::OR: - if (!MVT::isVector(VT)) - return getConstant(MVT::getIntVTBitMask(VT), VT); + if (!VT.isVector()) + return getConstant(VT.getIntegerVTBitMask(), VT); // For vectors, we can't easily build an all one vector, just return // the LHS. return N1; @@ -2437,7 +2431,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, return SDOperand(N, 0); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3) { // Perform various simplifications. ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); @@ -2469,9 +2463,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, break; case ISD::VECTOR_SHUFFLE: assert(VT == N1.getValueType() && VT == N2.getValueType() && - MVT::isVector(VT) && MVT::isVector(N3.getValueType()) && + VT.isVector() && N3.getValueType().isVector() && N3.getOpcode() == ISD::BUILD_VECTOR && - MVT::getVectorNumElements(VT) == N3.getNumOperands() && + VT.getVectorNumElements() == N3.getNumOperands() && "Illegal VECTOR_SHUFFLE node!"); break; case ISD::BIT_CONVERT: @@ -2500,14 +2494,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, return SDOperand(N, 0); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4) { SDOperand Ops[] = { N1, N2, N3, N4 }; return getNode(Opcode, VT, Ops, 4); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4, SDOperand N5) { SDOperand Ops[] = { N1, N2, N3, N4, N5 }; @@ -2516,10 +2510,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, /// getMemsetValue - Vectorized representation of the memset value /// operand. -static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, - SelectionDAG &DAG) { - unsigned NumBits = MVT::isVector(VT) ? - MVT::getSizeInBits(MVT::getVectorElementType(VT)) : MVT::getSizeInBits(VT); +static SDOperand getMemsetValue(SDOperand Value, MVT VT, SelectionDAG &DAG) { + unsigned NumBits = VT.isVector() ? + VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { APInt Val = APInt(NumBits, C->getValue() & 255); unsigned Shift = 8; @@ -2527,7 +2520,7 @@ static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, Val = (Val << Shift) | Val; Shift <<= 1; } - if (MVT::isInteger(VT)) + if (VT.isInteger()) return DAG.getConstant(Val, VT); return DAG.getConstantFP(APFloat(Val), VT); } @@ -2547,11 +2540,11 @@ static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, /// getMemsetStringVal - Similar to getMemsetValue. Except this is only /// used when a memcpy is turned into a memset when the source is a constant /// string ptr. -static SDOperand getMemsetStringVal(MVT::ValueType VT, SelectionDAG &DAG, +static SDOperand getMemsetStringVal(MVT VT, SelectionDAG &DAG, const TargetLowering &TLI, std::string &Str, unsigned Offset) { - assert(!MVT::isVector(VT) && "Can't handle vector type here!"); - unsigned NumBits = MVT::getSizeInBits(VT); + assert(!VT.isVector() && "Can't handle vector type here!"); + unsigned NumBits = VT.getSizeInBits(); unsigned MSB = NumBits / 8; uint64_t Val = 0; if (TLI.isLittleEndian()) @@ -2567,7 +2560,7 @@ static SDOperand getMemsetStringVal(MVT::ValueType VT, SelectionDAG &DAG, /// static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, SelectionDAG &DAG) { - MVT::ValueType VT = Base.getValueType(); + MVT VT = Base.getValueType(); return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); } @@ -2604,7 +2597,7 @@ static bool isMemSrcFromString(SDOperand Src, std::string &Str, /// to replace the memset / memcpy is below the threshold. It also returns the /// types of the sequence of memory ops to perform memset / memcpy. static -bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, +bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, SDOperand Dst, SDOperand Src, unsigned Limit, uint64_t Size, unsigned &Align, SelectionDAG &DAG, @@ -2615,10 +2608,10 @@ bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, uint64_t SrcOff = 0; bool isSrcStr = isMemSrcFromString(Src, Str, SrcOff); bool isSrcConst = isa<ConstantSDNode>(Src); - MVT::ValueType VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); + MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); if (VT != MVT::iAny) { unsigned NewAlign = (unsigned) - TLI.getTargetData()->getABITypeAlignment(MVT::getTypeForValueType(VT)); + TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); // If source is a string constant, this will require an unaligned load. if (NewAlign > Align && (isSrcConst || AllowUnalign)) { if (Dst.getOpcode() != ISD::FrameIndex) { @@ -2654,10 +2647,10 @@ bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, } } - MVT::ValueType LVT = MVT::i64; + MVT LVT = MVT::i64; while (!TLI.isTypeLegal(LVT)) - LVT = (MVT::ValueType)((unsigned)LVT - 1); - assert(MVT::isInteger(LVT)); + LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); + assert(LVT.isInteger()); if (VT > LVT) VT = LVT; @@ -2665,16 +2658,16 @@ bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps, unsigned NumMemOps = 0; while (Size != 0) { - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + unsigned VTSize = VT.getSizeInBits() / 8; while (VTSize > Size) { // For now, only use non-vector load / store's for the left-over pieces. - if (MVT::isVector(VT)) { + if (VT.isVector()) { VT = MVT::i64; while (!TLI.isTypeLegal(VT)) - VT = (MVT::ValueType)((unsigned)VT - 1); - VTSize = MVT::getSizeInBits(VT) / 8; + VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); + VTSize = VT.getSizeInBits() / 8; } else { - VT = (MVT::ValueType)((unsigned)VT - 1); + VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); VTSize >>= 1; } } @@ -2698,7 +2691,7 @@ static SDOperand getMemcpyLoadsAndStores(SelectionDAG &DAG, // Expand memcpy to a series of load and store ops if the size operand falls // below a certain threshold. - std::vector<MVT::ValueType> MemOps; + std::vector<MVT> MemOps; uint64_t Limit = -1; if (!AlwaysInline) Limit = TLI.getMaxStoresPerMemcpy(); @@ -2714,11 +2707,11 @@ static SDOperand getMemcpyLoadsAndStores(SelectionDAG &DAG, SmallVector<SDOperand, 8> OutChains; unsigned NumMemOps = MemOps.size(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT::ValueType VT = MemOps[i]; - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + MVT VT = MemOps[i]; + unsigned VTSize = VT.getSizeInBits() / 8; SDOperand Value, Store; - if (CopyFromStr && !MVT::isVector(VT)) { + if (CopyFromStr && !VT.isVector()) { // It's unlikely a store of a vector immediate can be done in a single // instruction. It would require a load from a constantpool first. // FIXME: Handle cases where store of vector immediate is done in a @@ -2754,7 +2747,7 @@ static SDOperand getMemmoveLoadsAndStores(SelectionDAG &DAG, // Expand memmove to a series of load and store ops if the size operand falls // below a certain threshold. - std::vector<MVT::ValueType> MemOps; + std::vector<MVT> MemOps; uint64_t Limit = -1; if (!AlwaysInline) Limit = TLI.getMaxStoresPerMemmove(); @@ -2770,8 +2763,8 @@ static SDOperand getMemmoveLoadsAndStores(SelectionDAG &DAG, SmallVector<SDOperand, 8> OutChains; unsigned NumMemOps = MemOps.size(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT::ValueType VT = MemOps[i]; - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + MVT VT = MemOps[i]; + unsigned VTSize = VT.getSizeInBits() / 8; SDOperand Value, Store; Value = DAG.getLoad(VT, Chain, @@ -2785,8 +2778,8 @@ static SDOperand getMemmoveLoadsAndStores(SelectionDAG &DAG, &LoadChains[0], LoadChains.size()); OutChains.clear(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT::ValueType VT = MemOps[i]; - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + MVT VT = MemOps[i]; + unsigned VTSize = VT.getSizeInBits() / 8; SDOperand Value, Store; Store = DAG.getStore(Chain, LoadValues[i], @@ -2809,7 +2802,7 @@ static SDOperand getMemsetStores(SelectionDAG &DAG, // Expand memset to a series of load/store ops if the size operand // falls below a certain threshold. - std::vector<MVT::ValueType> MemOps; + std::vector<MVT> MemOps; if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), Size, Align, DAG, TLI)) return SDOperand(); @@ -2819,8 +2812,8 @@ static SDOperand getMemsetStores(SelectionDAG &DAG, unsigned NumMemOps = MemOps.size(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT::ValueType VT = MemOps[i]; - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + MVT VT = MemOps[i]; + unsigned VTSize = VT.getSizeInBits() / 8; SDOperand Value = getMemsetValue(Src, VT, DAG); SDOperand Store = DAG.getStore(Chain, Value, getMemBasePlusOffset(Dst, DstOff, DAG), @@ -2984,14 +2977,14 @@ SDOperand SelectionDAG::getMemset(SDOperand Chain, SDOperand Dst, SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr, SDOperand Cmp, - SDOperand Swp, MVT::ValueType VT) { + SDOperand Swp, MVT VT) { assert(Opcode == ISD::ATOMIC_LCS && "Invalid Atomic Op"); assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); SDVTList VTs = getVTList(Cmp.getValueType(), MVT::Other); FoldingSetNodeID ID; SDOperand Ops[] = {Chain, Ptr, Cmp, Swp}; AddNodeIDNode(ID, Opcode, VTs, Ops, 4); - ID.AddInteger((unsigned int)VT); + ID.AddInteger(VT.V); void* IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); @@ -3003,7 +2996,7 @@ SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr, SDOperand Val, - MVT::ValueType VT) { + MVT VT) { assert(( Opcode == ISD::ATOMIC_LAS || Opcode == ISD::ATOMIC_LSS || Opcode == ISD::ATOMIC_SWAP || Opcode == ISD::ATOMIC_LOAD_AND || Opcode == ISD::ATOMIC_LOAD_OR || Opcode == ISD::ATOMIC_LOAD_XOR @@ -3014,7 +3007,7 @@ SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, FoldingSetNodeID ID; SDOperand Ops[] = {Chain, Ptr, Val}; AddNodeIDNode(ID, Opcode, VTs, Ops, 3); - ID.AddInteger((unsigned int)VT); + ID.AddInteger(VT.V); void* IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); @@ -3026,14 +3019,14 @@ SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, SDOperand SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT::ValueType VT, SDOperand Chain, + MVT VT, SDOperand Chain, SDOperand Ptr, SDOperand Offset, - const Value *SV, int SVOffset, MVT::ValueType EVT, + const Value *SV, int SVOffset, MVT EVT, bool isVolatile, unsigned Alignment) { if (Alignment == 0) { // Ensure that codegen never sees alignment 0 const Type *Ty = 0; if (VT != MVT::iPTR) { - Ty = MVT::getTypeForValueType(VT); + Ty = VT.getTypeForMVT(); } else if (SV) { const PointerType *PT = dyn_cast<PointerType>(SV->getType()); assert(PT && "Value for load must be a pointer"); @@ -3049,14 +3042,14 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, assert(VT == EVT && "Non-extending load from different memory type!"); } else { // Extending load. - if (MVT::isVector(VT)) - assert(EVT == MVT::getVectorElementType(VT) && "Invalid vector extload!"); + if (VT.isVector()) + assert(EVT == VT.getVectorElementType() && "Invalid vector extload!"); else - assert(MVT::getSizeInBits(EVT) < MVT::getSizeInBits(VT) && + assert(EVT.getSizeInBits() < VT.getSizeInBits() && "Should only be an extending load, not truncating!"); - assert((ExtType == ISD::EXTLOAD || MVT::isInteger(VT)) && + assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && "Cannot sign/zero extend a FP/Vector load!"); - assert(MVT::isInteger(VT) == MVT::isInteger(EVT) && + assert(VT.isInteger() == EVT.isInteger() && "Cannot convert from FP to Int or Int -> FP!"); } @@ -3071,7 +3064,7 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); ID.AddInteger(AM); ID.AddInteger(ExtType); - ID.AddInteger((unsigned int)EVT); + ID.AddInteger(EVT.V); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3084,7 +3077,7 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, return SDOperand(N, 0); } -SDOperand SelectionDAG::getLoad(MVT::ValueType VT, +SDOperand SelectionDAG::getLoad(MVT VT, SDOperand Chain, SDOperand Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { @@ -3093,10 +3086,10 @@ SDOperand SelectionDAG::getLoad(MVT::ValueType VT, SV, SVOffset, VT, isVolatile, Alignment); } -SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT, +SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, SDOperand Chain, SDOperand Ptr, const Value *SV, - int SVOffset, MVT::ValueType EVT, + int SVOffset, MVT EVT, bool isVolatile, unsigned Alignment) { SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType()); return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, @@ -3118,12 +3111,12 @@ SelectionDAG::getIndexedLoad(SDOperand OrigLoad, SDOperand Base, SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Val, SDOperand Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { - MVT::ValueType VT = Val.getValueType(); + MVT VT = Val.getValueType(); if (Alignment == 0) { // Ensure that codegen never sees alignment 0 const Type *Ty = 0; if (VT != MVT::iPTR) { - Ty = MVT::getTypeForValueType(VT); + Ty = VT.getTypeForMVT(); } else if (SV) { const PointerType *PT = dyn_cast<PointerType>(SV->getType()); assert(PT && "Value for store must be a pointer"); @@ -3139,7 +3132,7 @@ SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Val, AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(ISD::UNINDEXED); ID.AddInteger(false); - ID.AddInteger((unsigned int)VT); + ID.AddInteger(VT.V); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3154,22 +3147,22 @@ SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Val, SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Val, SDOperand Ptr, const Value *SV, - int SVOffset, MVT::ValueType SVT, + int SVOffset, MVT SVT, bool isVolatile, unsigned Alignment) { - MVT::ValueType VT = Val.getValueType(); + MVT VT = Val.getValueType(); if (VT == SVT) return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); - assert(MVT::getSizeInBits(VT) > MVT::getSizeInBits(SVT) && + assert(VT.getSizeInBits() > SVT.getSizeInBits() && "Not a truncation?"); - assert(MVT::isInteger(VT) == MVT::isInteger(SVT) && + assert(VT.isInteger() == SVT.isInteger() && "Can't do FP-INT conversion!"); if (Alignment == 0) { // Ensure that codegen never sees alignment 0 const Type *Ty = 0; if (VT != MVT::iPTR) { - Ty = MVT::getTypeForValueType(VT); + Ty = VT.getTypeForMVT(); } else if (SV) { const PointerType *PT = dyn_cast<PointerType>(SV->getType()); assert(PT && "Value for store must be a pointer"); @@ -3185,7 +3178,7 @@ SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Val, AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(ISD::UNINDEXED); ID.AddInteger(1); - ID.AddInteger((unsigned int)SVT); + ID.AddInteger(SVT.V); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3210,7 +3203,7 @@ SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base, AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(AM); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger((unsigned int)(ST->getMemoryVT())); + ID.AddInteger(ST->getMemoryVT().V); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); void *IP = 0; @@ -3225,14 +3218,14 @@ SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base, return SDOperand(N, 0); } -SDOperand SelectionDAG::getVAArg(MVT::ValueType VT, +SDOperand SelectionDAG::getVAArg(MVT VT, SDOperand Chain, SDOperand Ptr, SDOperand SV) { SDOperand Ops[] = { Chain, Ptr, SV }; return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperandPtr Ops, unsigned NumOps) { switch (NumOps) { case 0: return getNode(Opcode, VT); @@ -3281,14 +3274,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, } SDOperand SelectionDAG::getNode(unsigned Opcode, - std::vector<MVT::ValueType> &ResultTys, + std::vector<MVT> &ResultTys, SDOperandPtr Ops, unsigned NumOps) { return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), Ops, NumOps); } SDOperand SelectionDAG::getNode(unsigned Opcode, - const MVT::ValueType *VTs, unsigned NumVTs, + const MVT *VTs, unsigned NumVTs, SDOperandPtr Ops, unsigned NumOps) { if (NumVTs == 1) return getNode(Opcode, VTs[0], Ops, NumOps); @@ -3315,7 +3308,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { // If the and is only masking out bits that cannot effect the shift, // eliminate the and. - unsigned NumBits = MVT::getSizeInBits(VT)*2; + unsigned NumBits = VT.getSizeInBits()*2; if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); } @@ -3390,31 +3383,31 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, return getNode(Opcode, VTList, Ops, 5); } -SDVTList SelectionDAG::getVTList(MVT::ValueType VT) { +SDVTList SelectionDAG::getVTList(MVT VT) { return makeVTList(SDNode::getValueTypeList(VT), 1); } -SDVTList SelectionDAG::getVTList(MVT::ValueType VT1, MVT::ValueType VT2) { - for (std::list<std::vector<MVT::ValueType> >::iterator I = VTList.begin(), +SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { + for (std::list<std::vector<MVT> >::iterator I = VTList.begin(), E = VTList.end(); I != E; ++I) { if (I->size() == 2 && (*I)[0] == VT1 && (*I)[1] == VT2) return makeVTList(&(*I)[0], 2); } - std::vector<MVT::ValueType> V; + std::vector<MVT> V; V.push_back(VT1); V.push_back(VT2); VTList.push_front(V); return makeVTList(&(*VTList.begin())[0], 2); } -SDVTList SelectionDAG::getVTList(MVT::ValueType VT1, MVT::ValueType VT2, - MVT::ValueType VT3) { - for (std::list<std::vector<MVT::ValueType> >::iterator I = VTList.begin(), +SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, + MVT VT3) { + for (std::list<std::vector<MVT> >::iterator I = VTList.begin(), E = VTList.end(); I != E; ++I) { if (I->size() == 3 && (*I)[0] == VT1 && (*I)[1] == VT2 && (*I)[2] == VT3) return makeVTList(&(*I)[0], 3); } - std::vector<MVT::ValueType> V; + std::vector<MVT> V; V.push_back(VT1); V.push_back(VT2); V.push_back(VT3); @@ -3422,7 +3415,7 @@ SDVTList SelectionDAG::getVTList(MVT::ValueType VT1, MVT::ValueType VT2, return makeVTList(&(*VTList.begin())[0], 3); } -SDVTList SelectionDAG::getVTList(const MVT::ValueType *VTs, unsigned NumVTs) { +SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { switch (NumVTs) { case 0: assert(0 && "Cannot have nodes without results!"); case 1: return getVTList(VTs[0]); @@ -3431,7 +3424,7 @@ SDVTList SelectionDAG::getVTList(const MVT::ValueType *VTs, unsigned NumVTs) { default: break; } - for (std::list<std::vector<MVT::ValueType> >::iterator I = VTList.begin(), + for (std::list<std::vector<MVT> >::iterator I = VTList.begin(), E = VTList.end(); I != E; ++I) { if (I->size() != NumVTs || VTs[0] != (*I)[0] || VTs[1] != (*I)[1]) continue; @@ -3445,7 +3438,7 @@ SDVTList SelectionDAG::getVTList(const MVT::ValueType *VTs, unsigned NumVTs) { return makeVTList(&*I->begin(), NumVTs); } - VTList.push_front(std::vector<MVT::ValueType>(VTs, VTs+NumVTs)); + VTList.push_front(std::vector<MVT>(VTs, VTs+NumVTs)); return makeVTList(&*VTList.begin()->begin(), NumVTs); } @@ -3628,7 +3621,7 @@ void SDNode::MorphNodeTo(unsigned Opc, SDVTList L, /// node of the specified opcode and operands, it returns that node instead of /// the current one. SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT) { + MVT VT) { SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::BUILTIN_OP_END+TargetOpc, VTs, (SDOperand*)0, 0); @@ -3645,7 +3638,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT, SDOperand Op1) { + MVT VT, SDOperand Op1) { // If an identical node already exists, use it. SDVTList VTs = getVTList(VT); SDOperand Ops[] = { Op1 }; @@ -3663,7 +3656,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT, SDOperand Op1, + MVT VT, SDOperand Op1, SDOperand Op2) { // If an identical node already exists, use it. SDVTList VTs = getVTList(VT); @@ -3684,7 +3677,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT, SDOperand Op1, + MVT VT, SDOperand Op1, SDOperand Op2, SDOperand Op3) { // If an identical node already exists, use it. SDVTList VTs = getVTList(VT); @@ -3704,7 +3697,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT, SDOperandPtr Ops, + MVT VT, SDOperandPtr Ops, unsigned NumOps) { // If an identical node already exists, use it. SDVTList VTs = getVTList(VT); @@ -3722,7 +3715,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT1, MVT::ValueType VT2, + MVT VT1, MVT VT2, SDOperand Op1, SDOperand Op2) { SDVTList VTs = getVTList(VT1, VT2); FoldingSetNodeID ID; @@ -3739,7 +3732,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT1, MVT::ValueType VT2, + MVT VT1, MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3) { // If an identical node already exists, use it. @@ -3765,94 +3758,87 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, /// Note that getTargetNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT) { +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, - SDOperand Op1) { +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2, SDOperand Op3) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperandPtr Ops, unsigned NumOps) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, NumOps).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { + const MVT *VTs = getNodeValueTypes(VT1, VT2); SDOperand Op; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, &Op, 0).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, SDOperand Op1) { + const MVT *VTs = getNodeValueTypes(VT1, VT2); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, &Op1, 1).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, SDOperand Op1, SDOperand Op2) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); + const MVT *VTs = getNodeValueTypes(VT1, VT2); SDOperand Ops[] = { Op1, Op2 }; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, Ops, 2).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); + const MVT *VTs = getNodeValueTypes(VT1, VT2); SDOperand Ops[] = { Op1, Op2, Op3 }; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, Ops, 3).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDOperandPtr Ops, unsigned NumOps) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); + const MVT *VTs = getNodeValueTypes(VT1, VT2); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, Ops, NumOps).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperand Op1, SDOperand Op2) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2, VT3); + const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); SDOperand Ops[] = { Op1, Op2 }; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 3, Ops, 2).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperand Op1, SDOperand Op2, SDOperand Op3) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2, VT3); + const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); SDOperand Ops[] = { Op1, Op2, Op3 }; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 3, Ops, 3).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperandPtr Ops, unsigned NumOps) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2, VT3); + const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 3, Ops, NumOps).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, - MVT::ValueType VT4, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, MVT VT3, MVT VT4, SDOperandPtr Ops, unsigned NumOps) { - std::vector<MVT::ValueType> VTList; + std::vector<MVT> VTList; VTList.push_back(VT1); VTList.push_back(VT2); VTList.push_back(VT3); VTList.push_back(VT4); - const MVT::ValueType *VTs = getNodeValueTypes(VTList); + const MVT *VTs = getNodeValueTypes(VTList); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 4, Ops, NumOps).Val; } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, - std::vector<MVT::ValueType> &ResultTys, + std::vector<MVT> &ResultTys, SDOperandPtr Ops, unsigned NumOps) { - const MVT::ValueType *VTs = getNodeValueTypes(ResultTys); + const MVT *VTs = getNodeValueTypes(ResultTys); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, ResultTys.size(), Ops, NumOps).Val; } @@ -4200,7 +4186,7 @@ HandleSDNode::~HandleSDNode() { } GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, - MVT::ValueType VT, int o) + MVT VT, int o) : SDNode(isa<GlobalVariable>(GA) && cast<GlobalVariable>(GA)->isThreadLocal() ? // Thread Local @@ -4214,7 +4200,7 @@ GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, /// getMemOperand - Return a MachineMemOperand object describing the memory /// reference performed by this load or store. MachineMemOperand LSBaseSDNode::getMemOperand() const { - int Size = (MVT::getSizeInBits(getMemoryVT()) + 7) >> 3; + int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; int Flags = getOpcode() == ISD::LOAD ? MachineMemOperand::MOLoad : MachineMemOperand::MOStore; @@ -4240,14 +4226,14 @@ void SDNode::Profile(FoldingSetNodeID &ID) { /// getValueTypeList - Return a pointer to the specified value type. /// -const MVT::ValueType *SDNode::getValueTypeList(MVT::ValueType VT) { - if (MVT::isExtendedVT(VT)) { - static std::set<MVT::ValueType> EVTs; +const MVT *SDNode::getValueTypeList(MVT VT) { + if (VT.isExtended()) { + static std::set<MVT> EVTs; return &(*EVTs.insert(VT).first); } else { - static MVT::ValueType VTs[MVT::LAST_VALUETYPE]; - VTs[VT] = VT; - return &VTs[VT]; + static MVT VTs[MVT::LAST_VALUETYPE]; + VTs[VT.getSimpleVT()] = VT; + return &VTs[VT.getSimpleVT()]; } } @@ -4684,7 +4670,7 @@ void SDNode::dump(const SelectionDAG *G) const { if (getValueType(i) == MVT::Other) cerr << "ch"; else - cerr << MVT::getValueTypeString(getValueType(i)); + cerr << getValueType(i).getMVTString(); } cerr << " = " << getOperationName(G); @@ -4773,7 +4759,7 @@ void SDNode::dump(const SelectionDAG *G) const { } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { cerr << N->getArgFlags().getArgFlagsString(); } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { - cerr << ":" << MVT::getValueTypeString(N->getVT()); + cerr << ":" << N->getVT().getMVTString(); } else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { const Value *SrcValue = LD->getSrcValue(); int SrcOffset = LD->getSrcValueOffset(); @@ -4798,7 +4784,7 @@ void SDNode::dump(const SelectionDAG *G) const { break; } if (doExt) - cerr << MVT::getValueTypeString(LD->getMemoryVT()) << ">"; + cerr << LD->getMemoryVT().getMVTString() << ">"; const char *AM = getIndexedModeName(LD->getAddressingMode()); if (*AM) @@ -4818,7 +4804,7 @@ void SDNode::dump(const SelectionDAG *G) const { if (ST->isTruncatingStore()) cerr << " <trunc " - << MVT::getValueTypeString(ST->getMemoryVT()) << ">"; + << ST->getMemoryVT().getMVTString() << ">"; const char *AM = getIndexedModeName(ST->getAddressingMode()); if (*AM) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index a76e514f887..1dc6753268f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -88,10 +88,10 @@ defaultListDAGScheduler("default", " Best scheduler for the target", namespace { struct SDISelAsmOperandInfo; } /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of -/// MVT::ValueTypes that represent all the individual underlying +/// MVTs that represent all the individual underlying /// non-aggregate types that comprise it. static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, - SmallVectorImpl<MVT::ValueType> &ValueVTs) { + SmallVectorImpl<MVT> &ValueVTs) { // Given a struct type, recursively traverse the elements. if (const StructType *STy = dyn_cast<StructType>(Ty)) { for (StructType::element_iterator EI = STy->element_begin(), @@ -107,7 +107,7 @@ static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, ComputeValueVTs(TLI, EltTy, ValueVTs); return; } - // Base case: we can get an MVT::ValueType for this LLVM IR type. + // Base case: we can get an MVT for this LLVM IR type. ValueVTs.push_back(TLI.getValueType(Ty)); } @@ -129,7 +129,7 @@ namespace { /// ValueVTs - The value types of the values, which may not be legal, and /// may need be promoted or synthesized from one or more registers. /// - SmallVector<MVT::ValueType, 4> ValueVTs; + SmallVector<MVT, 4> ValueVTs; /// RegVTs - The value types of the registers. This is the same size as /// ValueVTs and it records, for each value, what the type of the assigned @@ -140,7 +140,7 @@ namespace { /// getRegisterType member function, however when with physical registers /// it is necessary to have a separate record of the types. /// - SmallVector<MVT::ValueType, 4> RegVTs; + SmallVector<MVT, 4> RegVTs; /// Regs - This list holds the registers assigned to the values. /// Each legal or promoted value requires one register, and each @@ -152,21 +152,21 @@ namespace { RegsForValue(const TargetLowering &tli, const SmallVector<unsigned, 4> ®s, - MVT::ValueType regvt, MVT::ValueType valuevt) + MVT regvt, MVT valuevt) : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} RegsForValue(const TargetLowering &tli, const SmallVector<unsigned, 4> ®s, - const SmallVector<MVT::ValueType, 4> ®vts, - const SmallVector<MVT::ValueType, 4> &valuevts) + const SmallVector<MVT, 4> ®vts, + const SmallVector<MVT, 4> &valuevts) : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} RegsForValue(const TargetLowering &tli, unsigned Reg, const Type *Ty) : TLI(&tli) { ComputeValueVTs(tli, Ty, ValueVTs); for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT::ValueType ValueVT = ValueVTs[Value]; + MVT ValueVT = ValueVTs[Value]; unsigned NumRegs = TLI->getNumRegisters(ValueVT); - MVT::ValueType RegisterVT = TLI->getRegisterType(ValueVT); + MVT RegisterVT = TLI->getRegisterType(ValueVT); for (unsigned i = 0; i != NumRegs; ++i) Regs.push_back(Reg + i); RegVTs.push_back(RegisterVT); @@ -254,7 +254,7 @@ namespace llvm { SmallSet<Instruction*, 8> CatchInfoFound; #endif - unsigned MakeReg(MVT::ValueType VT) { + unsigned MakeReg(MVT VT) { return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); } @@ -359,7 +359,7 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){ if (PN->use_empty()) continue; - MVT::ValueType VT = TLI.getValueType(PN->getType()); + MVT VT = TLI.getValueType(PN->getType()); unsigned NumRegisters = TLI.getNumRegisters(VT); unsigned PHIReg = ValueMap[PN]; assert(PHIReg && "PHI node does not have an assigned virtual register!"); @@ -378,13 +378,13 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, /// will assign registers for each member or element. /// unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { - SmallVector<MVT::ValueType, 4> ValueVTs; + SmallVector<MVT, 4> ValueVTs; ComputeValueVTs(TLI, V->getType(), ValueVTs); unsigned FirstReg = 0; for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT::ValueType ValueVT = ValueVTs[Value]; - MVT::ValueType RegisterVT = TLI.getRegisterType(ValueVT); + MVT ValueVT = ValueVTs[Value]; + MVT RegisterVT = TLI.getRegisterType(ValueVT); unsigned NumRegs = TLI.getNumRegisters(ValueVT); for (unsigned i = 0; i != NumRegs; ++i) { @@ -751,8 +751,8 @@ private: static SDOperand getCopyFromParts(SelectionDAG &DAG, const SDOperand *Parts, unsigned NumParts, - MVT::ValueType PartVT, - MVT::ValueType ValueVT, + MVT PartVT, + MVT ValueVT, ISD::NodeType AssertOp = ISD::DELETED_NODE) { assert(NumParts > 0 && "No parts to assemble!"); TargetLowering &TLI = DAG.getTargetLoweringInfo(); @@ -760,20 +760,20 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, if (NumParts > 1) { // Assemble the value from multiple parts. - if (!MVT::isVector(ValueVT)) { - unsigned PartBits = MVT::getSizeInBits(PartVT); - unsigned ValueBits = MVT::getSizeInBits(ValueVT); + if (!ValueVT.isVector()) { + unsigned PartBits = PartVT.getSizeInBits(); + unsigned ValueBits = ValueVT.getSizeInBits(); // Assemble the power of 2 part. unsigned RoundParts = NumParts & (NumParts - 1) ? 1 << Log2_32(NumParts) : NumParts; unsigned RoundBits = PartBits * RoundParts; - MVT::ValueType RoundVT = RoundBits == ValueBits ? - ValueVT : MVT::getIntegerType(RoundBits); + MVT RoundVT = RoundBits == ValueBits ? + ValueVT : MVT::getIntegerVT(RoundBits); SDOperand Lo, Hi; if (RoundParts > 2) { - MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2); + MVT HalfVT = MVT::getIntegerVT(RoundBits/2); Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, PartVT, HalfVT); @@ -788,24 +788,24 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, if (RoundParts < NumParts) { // Assemble the trailing non-power-of-2 part. unsigned OddParts = NumParts - RoundParts; - MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits); + MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); // Combine the round and odd parts. Lo = Val; if (TLI.isBigEndian()) std::swap(Lo, Hi); - MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits); + MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, - DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()), + DAG.getConstant(Lo.getValueType().getSizeInBits(), TLI.getShiftAmountTy())); Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); } } else { // Handle a multi-element vector. - MVT::ValueType IntermediateVT, RegisterVT; + MVT IntermediateVT, RegisterVT; unsigned NumIntermediates; unsigned NumRegs = TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, @@ -837,7 +837,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate // operands. - Val = DAG.getNode(MVT::isVector(IntermediateVT) ? + Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, ValueVT, &Ops[0], NumIntermediates); } @@ -849,21 +849,21 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, if (PartVT == ValueVT) return Val; - if (MVT::isVector(PartVT)) { - assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); + if (PartVT.isVector()) { + assert(ValueVT.isVector() && "Unknown vector conversion!"); return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); } - if (MVT::isVector(ValueVT)) { - assert(MVT::getVectorElementType(ValueVT) == PartVT && - MVT::getVectorNumElements(ValueVT) == 1 && + if (ValueVT.isVector()) { + assert(ValueVT.getVectorElementType() == PartVT && + ValueVT.getVectorNumElements() == 1 && "Only trivial scalar-to-vector conversions should get here!"); return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); } - if (MVT::isInteger(PartVT) && - MVT::isInteger(ValueVT)) { - if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) { + if (PartVT.isInteger() && + ValueVT.isInteger()) { + if (ValueVT.getSizeInBits() < PartVT.getSizeInBits()) { // For a truncate, see if we have any information to // indicate whether the truncated bits will always be // zero or sign-extension. @@ -876,7 +876,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, } } - if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) { + if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { if (ValueVT < Val.getValueType()) // FP_ROUND's are always exact here. return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, @@ -884,7 +884,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val); } - if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT)) + if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); assert(0 && "Unknown mismatch!"); @@ -898,43 +898,43 @@ static void getCopyToParts(SelectionDAG &DAG, SDOperand Val, SDOperand *Parts, unsigned NumParts, - MVT::ValueType PartVT, + MVT PartVT, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { TargetLowering &TLI = DAG.getTargetLoweringInfo(); - MVT::ValueType PtrVT = TLI.getPointerTy(); - MVT::ValueType ValueVT = Val.getValueType(); - unsigned PartBits = MVT::getSizeInBits(PartVT); + MVT PtrVT = TLI.getPointerTy(); + MVT ValueVT = Val.getValueType(); + unsigned PartBits = PartVT.getSizeInBits(); assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); if (!NumParts) return; - if (!MVT::isVector(ValueVT)) { + if (!ValueVT.isVector()) { if (PartVT == ValueVT) { assert(NumParts == 1 && "No-op copy with multiple parts!"); Parts[0] = Val; return; } - if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) { + if (NumParts * PartBits > ValueVT.getSizeInBits()) { // If the parts cover more bits than the value has, promote the value. - if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) { + if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { assert(NumParts == 1 && "Do not know what to promote to!"); Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); - } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { - ValueVT = MVT::getIntegerType(NumParts * PartBits); + } else if (PartVT.isInteger() && ValueVT.isInteger()) { + ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ExtendKind, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); } - } else if (PartBits == MVT::getSizeInBits(ValueVT)) { + } else if (PartBits == ValueVT.getSizeInBits()) { // Different types of the same size. assert(NumParts == 1 && PartVT != ValueVT); Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); - } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) { + } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { // If the parts cover less bits than value has, truncate the value. - if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { - ValueVT = MVT::getIntegerType(NumParts * PartBits); + if (PartVT.isInteger() && ValueVT.isInteger()) { + ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); @@ -943,7 +943,7 @@ static void getCopyToParts(SelectionDAG &DAG, // The value may have changed - recompute ValueVT. ValueVT = Val.getValueType(); - assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) && + assert(NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"); if (NumParts == 1) { @@ -955,7 +955,7 @@ static void getCopyToParts(SelectionDAG &DAG, // Expand the value into multiple parts. if (NumParts & (NumParts - 1)) { // The number of parts is not a power of 2. Split off and copy the tail. - assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) && + assert(PartVT.isInteger() && ValueVT.isInteger() && "Do not know what to expand to!"); unsigned RoundParts = 1 << Log2_32(NumParts); unsigned RoundBits = RoundParts * PartBits; @@ -968,19 +968,19 @@ static void getCopyToParts(SelectionDAG &DAG, // The odd parts were reversed by getCopyToParts - unreverse them. std::reverse(Parts + RoundParts, Parts + NumParts); NumParts = RoundParts; - ValueVT = MVT::getIntegerType(NumParts * PartBits); + ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); } // The number of parts is a power of 2. Repeatedly bisect the value using // EXTRACT_ELEMENT. Parts[0] = DAG.getNode(ISD::BIT_CONVERT, - MVT::getIntegerType(MVT::getSizeInBits(ValueVT)), + MVT::getIntegerVT(ValueVT.getSizeInBits()), Val); for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { for (unsigned i = 0; i < NumParts; i += StepSize) { unsigned ThisBits = StepSize * PartBits / 2; - MVT::ValueType ThisVT = MVT::getIntegerType (ThisBits); + MVT ThisVT = MVT::getIntegerVT (ThisBits); SDOperand &Part0 = Parts[i]; SDOperand &Part1 = Parts[i+StepSize/2]; @@ -1005,11 +1005,11 @@ static void getCopyToParts(SelectionDAG &DAG, // Vector ValueVT. if (NumParts == 1) { if (PartVT != ValueVT) { - if (MVT::isVector(PartVT)) { + if (PartVT.isVector()) { Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); } else { - assert(MVT::getVectorElementType(ValueVT) == PartVT && - MVT::getVectorNumElements(ValueVT) == 1 && + assert(ValueVT.getVectorElementType() == PartVT && + ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"); Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, DAG.getConstant(0, PtrVT)); @@ -1021,13 +1021,13 @@ static void getCopyToParts(SelectionDAG &DAG, } // Handle a multi-element vector. - MVT::ValueType IntermediateVT, RegisterVT; + MVT IntermediateVT, RegisterVT; unsigned NumIntermediates; unsigned NumRegs = DAG.getTargetLoweringInfo() .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, RegisterVT); - unsigned NumElements = MVT::getVectorNumElements(ValueVT); + unsigned NumElements = ValueVT.getVectorNumElements(); assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); NumParts = NumRegs; // Silence a compiler warning. @@ -1036,7 +1036,7 @@ static void getCopyToParts(SelectionDAG &DAG, // Split the vector into intermediate operands. SmallVector<SDOperand, 8> Ops(NumIntermediates); for (unsigned i = 0; i != NumIntermediates; ++i) - if (MVT::isVector(IntermediateVT)) + if (IntermediateVT.isVector()) Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, IntermediateVT, Val, DAG.getConstant(i * (NumElements / NumIntermediates), @@ -1069,7 +1069,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { if (N.Val) return N; if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { - MVT::ValueType VT = TLI.getValueType(V->getType(), true); + MVT VT = TLI.getValueType(V->getType(), true); if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) return N = DAG.getConstant(CI->getValue(), VT); @@ -1105,12 +1105,12 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { } else { assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && "Unknown vector constant!"); - MVT::ValueType EltVT = TLI.getValueType(VecTy->getElementType()); + MVT EltVT = TLI.getValueType(VecTy->getElementType()); SDOperand Op; if (isa<UndefValue>(C)) Op = DAG.getNode(ISD::UNDEF, EltVT); - else if (MVT::isFloatingPoint(EltVT)) + else if (EltVT.isFloatingPoint()) Op = DAG.getConstantFP(0, EltVT); else Op = DAG.getConstant(0, EltVT); @@ -1149,18 +1149,18 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { NewValues.push_back(getControlRoot()); for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { SDOperand RetOp = getValue(I.getOperand(i)); - MVT::ValueType VT = RetOp.getValueType(); + MVT VT = RetOp.getValueType(); // FIXME: C calling convention requires the return type to be promoted to // at least 32-bit. But this is not necessary for non-C calling conventions. - if (MVT::isInteger(VT)) { - MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32); - if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT)) + if (VT.isInteger()) { + MVT MinVT = TLI.getRegisterType(MVT::i32); + if (VT.getSizeInBits() < MinVT.getSizeInBits()) VT = MinVT; } unsigned NumParts = TLI.getNumRegisters(VT); - MVT::ValueType PartVT = TLI.getRegisterType(VT); + MVT PartVT = TLI.getRegisterType(VT); SmallVector<SDOperand, 4> Parts(NumParts); ISD::NodeType ExtendKind = ISD::ANY_EXTEND; @@ -1475,7 +1475,7 @@ void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue(); SDOperand CmpOp = getValue(CB.CmpMHS); - MVT::ValueType VT = CmpOp.getValueType(); + MVT VT = CmpOp.getValueType(); if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); @@ -1517,7 +1517,7 @@ void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) { void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { // Emit the code for the jump table assert(JT.Reg != -1U && "Should lower JT Header first!"); - MVT::ValueType PTy = TLI.getPointerTy(); + MVT PTy = TLI.getPointerTy(); SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), @@ -1533,7 +1533,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, // and conditional branch to default mbb if the result is greater than the // difference between smallest and largest cases. SDOperand SwitchOp = getValue(JTH.SValue); - MVT::ValueType VT = SwitchOp.getValueType(); + MVT VT = SwitchOp.getValueType(); SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, DAG.getConstant(JTH.First, VT)); @@ -1542,7 +1542,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, // register so it can be used as an index into the jump table in a // subsequent basic block. This value may be smaller or larger than the // target's pointer type, and therefore require extension or truncating. - if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) + if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits()) SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); else SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); @@ -1582,7 +1582,7 @@ void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT, void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { // Subtract the minimum value SDOperand SwitchOp = getValue(B.SValue); - MVT::ValueType VT = SwitchOp.getValueType(); + MVT VT = SwitchOp.getValueType(); SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, DAG.getConstant(B.First, VT)); @@ -1592,7 +1592,7 @@ void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) ISD::SETUGT); SDOperand ShiftOp; - if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) + if (VT.getSizeInBits() > TLI.getShiftAmountTy().getSizeInBits()) ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); else ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); @@ -2005,7 +2005,7 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, CaseRecVector& WorkList, Value* SV, MachineBasicBlock* Default){ - unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); + unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits(); Case& FrontCase = *CR.Range.first; Case& BackCase = *(CR.Range.second-1); @@ -2271,8 +2271,8 @@ void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { SDOperand Op1 = getValue(I.getOperand(0)); SDOperand Op2 = getValue(I.getOperand(1)); - if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < - MVT::getSizeInBits(Op2.getValueType())) + if (TLI.getShiftAmountTy().getSizeInBits() < + Op2.getValueType().getSizeInBits()) Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); else if (TLI.getShiftAmountTy() > Op2.getValueType()) Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); @@ -2410,7 +2410,7 @@ void SelectionDAGLowering::visitVFCmp(User &I) { else Condition = FPC; - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); } @@ -2427,7 +2427,7 @@ void SelectionDAGLowering::visitSelect(User &I) { void SelectionDAGLowering::visitTrunc(User &I) { // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); } @@ -2435,7 +2435,7 @@ void SelectionDAGLowering::visitZExt(User &I) { // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). // ZExt also can't be a cast to bool for same reason. So, nothing much to do SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); } @@ -2443,49 +2443,49 @@ void SelectionDAGLowering::visitSExt(User &I) { // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). // SExt also can't be a cast to bool for same reason. So, nothing much to do SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); } void SelectionDAGLowering::visitFPTrunc(User &I) { // FPTrunc is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); } void SelectionDAGLowering::visitFPExt(User &I){ // FPTrunc is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); } void SelectionDAGLowering::visitFPToUI(User &I) { // FPToUI is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); } void SelectionDAGLowering::visitFPToSI(User &I) { // FPToSI is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); } void SelectionDAGLowering::visitUIToFP(User &I) { // UIToFP is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); } void SelectionDAGLowering::visitSIToFP(User &I){ // UIToFP is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); } @@ -2493,10 +2493,10 @@ void SelectionDAGLowering::visitPtrToInt(User &I) { // What to do depends on the size of the integer and the size of the pointer. // We can either truncate, zero extend, or no-op, accordingly. SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType SrcVT = N.getValueType(); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT SrcVT = N.getValueType(); + MVT DestVT = TLI.getValueType(I.getType()); SDOperand Result; - if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) + if (DestVT.getSizeInBits() < SrcVT.getSizeInBits()) Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too @@ -2508,9 +2508,9 @@ void SelectionDAGLowering::visitIntToPtr(User &I) { // What to do depends on the size of the integer and the size of the pointer. // We can either truncate, zero extend, or no-op, accordingly. SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType SrcVT = N.getValueType(); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); - if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) + MVT SrcVT = N.getValueType(); + MVT DestVT = TLI.getValueType(I.getType()); + if (DestVT.getSizeInBits() < SrcVT.getSizeInBits()) setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too @@ -2519,7 +2519,7 @@ void SelectionDAGLowering::visitIntToPtr(User &I) { void SelectionDAGLowering::visitBitCast(User &I) { SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); // BitCast assures us that source and destination are the same size so this // is either a BIT_CONVERT or a no-op. @@ -2640,7 +2640,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) { I.getAlignment()); SDOperand AllocSize = getValue(I.getArraySize()); - MVT::ValueType IntPtr = TLI.getPointerTy(); + MVT IntPtr = TLI.getPointerTy(); if (IntPtr < AllocSize.getValueType()) AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); else if (IntPtr > AllocSize.getValueType()) @@ -2666,7 +2666,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) { DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; - const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), + const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), MVT::Other); SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); setValue(&I, DSA); @@ -2746,14 +2746,14 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, Ops.push_back(Op); } - std::vector<MVT::ValueType> VTs; + std::vector<MVT> VTs; if (I.getType() != Type::VoidTy) { - MVT::ValueType VT = TLI.getValueType(I.getType()); - if (MVT::isVector(VT)) { + MVT VT = TLI.getValueType(I.getType()); + if (VT.isVector()) { const VectorType *DestTy = cast<VectorType>(I.getType()); - MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); + MVT EltVT = TLI.getValueType(DestTy->getElementType()); - VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); + VT = MVT::getVectorVT(EltVT, DestTy->getNumElements()); assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); } @@ -2763,7 +2763,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, if (HasChain) VTs.push_back(MVT::Other); - const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); + const MVT *VTList = DAG.getNodeValueTypes(VTs); // Create the node. SDOperand Result; @@ -2786,7 +2786,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, } if (I.getType() != Type::VoidTy) { if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { - MVT::ValueType VT = TLI.getValueType(PTy); + MVT VT = TLI.getValueType(PTy); Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); } setValue(&I, Result); @@ -3038,7 +3038,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::eh_selector_i32: case Intrinsic::eh_selector_i64: { MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); - MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? + MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64); if (MMI) { @@ -3071,7 +3071,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::eh_typeid_for_i32: case Intrinsic::eh_typeid_for_i64: { MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); - MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? + MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? MVT::i32 : MVT::i64); if (MMI) { @@ -3114,9 +3114,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { } case Intrinsic::eh_dwarf_cfa: { - MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); + MVT VT = getValue(I.getOperand(1)).getValueType(); SDOperand CfaArg; - if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) + if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits()) CfaArg = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), getValue(I.getOperand(1))); else @@ -3196,21 +3196,21 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; case Intrinsic::cttz: { SDOperand Arg = getValue(I.getOperand(1)); - MVT::ValueType Ty = Arg.getValueType(); + MVT Ty = Arg.getValueType(); SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::ctlz: { SDOperand Arg = getValue(I.getOperand(1)); - MVT::ValueType Ty = Arg.getValueType(); + MVT Ty = Arg.getValueType(); SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::ctpop: { SDOperand Arg = getValue(I.getOperand(1)); - MVT::ValueType Ty = Arg.getValueType(); + MVT Ty = Arg.getValueType(); SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); setValue(&I, result); return 0; @@ -3503,9 +3503,9 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, SmallVector<SDOperand, 8> Parts; for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { // Copy the legal parts from the registers. - MVT::ValueType ValueVT = ValueVTs[Value]; + MVT ValueVT = ValueVTs[Value]; unsigned NumRegs = TLI->getNumRegisters(ValueVT); - MVT::ValueType RegisterVT = RegVTs[Value]; + MVT RegisterVT = RegVTs[Value]; Parts.resize(NumRegs); for (unsigned i = 0; i != NumRegs; ++i) { @@ -3543,9 +3543,9 @@ void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, unsigned NumRegs = Regs.size(); SmallVector<SDOperand, 8> Parts(NumRegs); for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT::ValueType ValueVT = ValueVTs[Value]; + MVT ValueVT = ValueVTs[Value]; unsigned NumParts = TLI->getNumRegisters(ValueVT); - MVT::ValueType RegisterVT = RegVTs[Value]; + MVT RegisterVT = RegVTs[Value]; getCopyToParts(DAG, Val.getValue(Val.ResNo + Value), &Parts[Part], NumParts, RegisterVT); @@ -3586,11 +3586,11 @@ void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, /// values added into it. void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, std::vector<SDOperand> &Ops) const { - MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); + MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]); - MVT::ValueType RegisterVT = RegVTs[Value]; + MVT RegisterVT = RegVTs[Value]; for (unsigned i = 0; i != NumRegs; ++i) Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); } @@ -3603,11 +3603,11 @@ static const TargetRegisterClass * isAllocatableRegister(unsigned Reg, MachineFunction &MF, const TargetLowering &TLI, const TargetRegisterInfo *TRI) { - MVT::ValueType FoundVT = MVT::Other; + MVT FoundVT = MVT::Other; const TargetRegisterClass *FoundRC = 0; for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), E = TRI->regclass_end(); RCI != E; ++RCI) { - MVT::ValueType ThisVT = MVT::Other; + MVT ThisVT = MVT::Other; const TargetRegisterClass *RC = *RCI; // If none of the the value types for this register class are valid, we @@ -3619,7 +3619,7 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF, // choose the one with the largest VT specified. For example, on // PowerPC, we favor f64 register classes over f32. if (FoundVT == MVT::Other || - MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { + FoundVT.getSizeInBits() < (*I).getSizeInBits()) { ThisVT = *I; break; } @@ -3745,8 +3745,8 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber, unsigned NumRegs = 1; if (OpInfo.ConstraintVT != MVT::Other) NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); - MVT::ValueType RegVT; - MVT::ValueType ValueVT = OpInfo.ConstraintVT; + MVT RegVT; + MVT ValueVT = OpInfo.ConstraintVT; // If this is a constraint for a specific physical register, like {r17}, @@ -3895,7 +3895,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); - MVT::ValueType OpVT = MVT::Other; + MVT OpVT = MVT::Other; // Compute the value type for each operand. switch (OpInfo.Type) { @@ -4227,12 +4227,12 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // bit_convert. if (const StructType *ResSTy = dyn_cast<StructType>(CS.getType())) { for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) { - if (MVT::isVector(Val.Val->getValueType(i))) + if (Val.Val->getValueType(i).isVector()) Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(ResSTy->getElementType(i)), Val); } } else { - if (MVT::isVector(Val.getValueType())) + if (Val.getValueType().isVector()) Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()), Val); } @@ -4267,7 +4267,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { void SelectionDAGLowering::visitMalloc(MallocInst &I) { SDOperand Src = getValue(I.getOperand(0)); - MVT::ValueType IntPtr = TLI.getPointerTy(); + MVT IntPtr = TLI.getPointerTy(); if (IntPtr < Src.getValueType()) Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); @@ -4298,7 +4298,7 @@ void SelectionDAGLowering::visitFree(FreeInst &I) { Entry.Node = getValue(I.getOperand(0)); Entry.Ty = TLI.getTargetData()->getIntPtrType(); Args.push_back(Entry); - MVT::ValueType IntPtr = TLI.getPointerTy(); + MVT IntPtr = TLI.getPointerTy(); std::pair<SDOperand,SDOperand> Result = TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, CallingConv::C, true, @@ -4361,11 +4361,11 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); // Add one result value for each formal argument. - std::vector<MVT::ValueType> RetVals; + std::vector<MVT> RetVals; unsigned j = 1; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I, ++j) { - MVT::ValueType VT = getValueType(I->getType()); + MVT VT = getValueType(I->getType()); ISD::ArgFlagsTy Flags; unsigned OriginalAlignment = getTargetData()->getABITypeAlignment(I->getType()); @@ -4395,7 +4395,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { Flags.setNest(); Flags.setOrigAlign(OriginalAlignment); - MVT::ValueType RegisterVT = getRegisterType(VT); + MVT RegisterVT = getRegisterType(VT); unsigned NumRegs = getNumRegisters(VT); for (unsigned i = 0; i != NumRegs; ++i) { RetVals.push_back(RegisterVT); @@ -4438,8 +4438,8 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { unsigned Idx = 1; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I, ++Idx) { - MVT::ValueType VT = getValueType(I->getType()); - MVT::ValueType PartVT = getRegisterType(VT); + MVT VT = getValueType(I->getType()); + MVT PartVT = getRegisterType(VT); unsigned NumParts = getNumRegisters(VT); SmallVector<SDOperand, 4> Parts(NumParts); @@ -4479,7 +4479,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, // Handle all of the outgoing arguments. for (unsigned i = 0, e = Args.size(); i != e; ++i) { - MVT::ValueType VT = getValueType(Args[i].Ty); + MVT VT = getValueType(Args[i].Ty); SDOperand Op = Args[i].Node; ISD::ArgFlagsTy Flags; unsigned OriginalAlignment = @@ -4510,7 +4510,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, Flags.setNest(); Flags.setOrigAlign(OriginalAlignment); - MVT::ValueType PartVT = getRegisterType(VT); + MVT PartVT = getRegisterType(VT); unsigned NumParts = getNumRegisters(VT); SmallVector<SDOperand, 4> Parts(NumParts); ISD::NodeType ExtendKind = ISD::ANY_EXTEND; @@ -4537,14 +4537,14 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, // Figure out the result value types. We start by making a list of // the potentially illegal return value types. - SmallVector<MVT::ValueType, 4> LoweredRetTys; - SmallVector<MVT::ValueType, 4> RetTys; + SmallVector<MVT, 4> LoweredRetTys; + SmallVector<MVT, 4> RetTys; ComputeValueVTs(*this, RetTy, RetTys); // Then we translate that to a list of legal types. for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { - MVT::ValueType VT = RetTys[I]; - MVT::ValueType RegisterVT = getRegisterType(VT); + MVT VT = RetTys[I]; + MVT RegisterVT = getRegisterType(VT); unsigned NumRegs = getNumRegisters(VT); for (unsigned i = 0; i != NumRegs; ++i) LoweredRetTys.push_back(RegisterVT); @@ -4571,8 +4571,8 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, SmallVector<SDOperand, 4> ReturnValues; unsigned RegNo = 0; for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { - MVT::ValueType VT = RetTys[I]; - MVT::ValueType RegisterVT = getRegisterType(VT); + MVT VT = RetTys[I]; + MVT RegisterVT = getRegisterType(VT); unsigned NumRegs = getNumRegisters(VT); unsigned RegNoEnd = NumRegs + RegNo; SmallVector<SDOperand, 4> Results; @@ -4609,7 +4609,7 @@ SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, // SelectionDAGISel code //===----------------------------------------------------------------------===// -unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { +unsigned SelectionDAGISel::MakeReg(MVT VT) { return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); } @@ -4798,7 +4798,7 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, MachineFrameInfo *MFI = MF.getFrameInfo(); if (!isByVal && IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { - MVT::ValueType VT = Arg.getValueType(); + MVT VT = Arg.getValueType(); unsigned VReg = MF.getRegInfo(). createVirtualRegister(TLI.getRegClassFor(VT)); Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); @@ -4951,7 +4951,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, // Remember that this register needs to added to the machine PHI node as // the input for this MBB. - MVT::ValueType VT = TLI.getValueType(PN->getType()); + MVT VT = TLI.getValueType(PN->getType()); unsigned NumRegisters = TLI.getNumRegisters(VT); for (unsigned i = 0, e = NumRegisters; i != e; ++i) PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); @@ -5356,7 +5356,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) { } // Add this to the output node. - MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); + MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), IntPtrTy)); Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index 904638d4f7a..f9221680198 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -48,7 +48,7 @@ namespace llvm { template<typename EdgeIter> static std::string getEdgeAttributes(const void *Node, EdgeIter EI) { SDOperand Op = EI.getNode()->getOperand(EI.getOperand()); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); if (VT == MVT::Flag) return "color=red,style=bold"; else if (VT == MVT::Other) @@ -90,7 +90,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node, if (Node->getValueType(i) == MVT::Other) Op += ":ch"; else - Op = Op + ":" + MVT::getValueTypeString(Node->getValueType(i)); + Op = Op + ":" + Node->getValueType(i).getMVTString(); if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(Node)) { Op += ": " + utostr(CSDN->getValue()); @@ -154,7 +154,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node, } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(Node)) { Op = Op + " AF=" + N->getArgFlags().getArgFlagsString(); } else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) { - Op = Op + " VT=" + MVT::getValueTypeString(N->getVT()); + Op = Op + " VT=" + N->getVT().getMVTString(); } else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) { Op = Op + "\"" + N->getValue() + "\""; } else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Node)) { @@ -172,7 +172,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node, break; } if (doExt) - Op += MVT::getValueTypeString(LD->getMemoryVT()) + ">"; + Op += LD->getMemoryVT().getMVTString() + ">"; if (LD->isVolatile()) Op += "<V>"; Op += LD->getIndexedModeName(LD->getAddressingMode()); @@ -180,7 +180,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node, Op += " A=" + utostr(LD->getAlignment()); } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Node)) { if (ST->isTruncatingStore()) - Op += "<trunc " + MVT::getValueTypeString(ST->getMemoryVT()) + ">"; + Op += "<trunc " + ST->getMemoryVT().getMVTString() + ">"; if (ST->isVolatile()) Op += "<V>"; Op += ST->getIndexedModeName(ST->getAddressingMode()); diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 408a5b23b4f..774988aa8b3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -180,12 +180,12 @@ TargetLowering::TargetLowering(TargetMachine &tm) // Default all indexed load / store to expand. for (unsigned IM = (unsigned)ISD::PRE_INC; IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { - setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); - setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); + setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); + setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); } // These operations default to expand. - setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); } // Most targets ignore the @llvm.prefetch intrinsic. @@ -244,7 +244,7 @@ void TargetLowering::computeRegisterProperties() { // Everything defaults to needing one register. for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { NumRegistersForVT[i] = 1; - RegisterTypeForVT[i] = TransformToType[i] = i; + RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; } // ...except isVoid, which doesn't need any registers. NumRegistersForVT[MVT::isVoid] = 0; @@ -256,24 +256,28 @@ void TargetLowering::computeRegisterProperties() { // Every integer value type larger than this largest register takes twice as // many registers to represent as the previous ValueType. - for (MVT::ValueType ExpandedReg = LargestIntReg + 1; - MVT::isInteger(ExpandedReg); ++ExpandedReg) { + for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { + MVT EVT = (MVT::SimpleValueType)ExpandedReg; + if (!EVT.isInteger()) + break; NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; - RegisterTypeForVT[ExpandedReg] = LargestIntReg; - TransformToType[ExpandedReg] = ExpandedReg - 1; - ValueTypeActions.setTypeAction(ExpandedReg, Expand); + RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; + TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); + ValueTypeActions.setTypeAction(EVT, Expand); } // Inspect all of the ValueType's smaller than the largest integer // register to see which ones need promotion. - MVT::ValueType LegalIntReg = LargestIntReg; - for (MVT::ValueType IntReg = LargestIntReg - 1; - IntReg >= MVT::i1; --IntReg) { - if (isTypeLegal(IntReg)) { + unsigned LegalIntReg = LargestIntReg; + for (unsigned IntReg = LargestIntReg - 1; + IntReg >= (unsigned)MVT::i1; --IntReg) { + MVT IVT = (MVT::SimpleValueType)IntReg; + if (isTypeLegal(IVT)) { LegalIntReg = IntReg; } else { - RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; - ValueTypeActions.setTypeAction(IntReg, Promote); + RegisterTypeForVT[IntReg] = TransformToType[IntReg] = + (MVT::SimpleValueType)LegalIntReg; + ValueTypeActions.setTypeAction(IVT, Promote); } } @@ -311,18 +315,19 @@ void TargetLowering::computeRegisterProperties() { } // Loop over all of the vector value types to see which need transformations. - for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; - i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { - if (!isTypeLegal(i)) { - MVT::ValueType IntermediateVT, RegisterVT; + for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; + i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { + MVT VT = (MVT::SimpleValueType)i; + if (!isTypeLegal(VT)) { + MVT IntermediateVT, RegisterVT; unsigned NumIntermediates; NumRegistersForVT[i] = - getVectorTypeBreakdown(i, + getVectorTypeBreakdown(VT, IntermediateVT, NumIntermediates, RegisterVT); RegisterTypeForVT[i] = RegisterVT; TransformToType[i] = MVT::Other; // this isn't actually used - ValueTypeActions.setTypeAction(i, Expand); + ValueTypeActions.setTypeAction(VT, Expand); } } } @@ -332,8 +337,7 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { } -MVT::ValueType -TargetLowering::getSetCCResultType(const SDOperand &) const { +MVT TargetLowering::getSetCCResultType(const SDOperand &) const { return getValueType(TD->getIntPtrType()); } @@ -347,13 +351,13 @@ TargetLowering::getSetCCResultType(const SDOperand &) const { /// register. It also returns the VT and quantity of the intermediate values /// before they are promoted/expanded. /// -unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, - MVT::ValueType &IntermediateVT, +unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, + MVT &IntermediateVT, unsigned &NumIntermediates, - MVT::ValueType &RegisterVT) const { + MVT &RegisterVT) const { // Figure out the right, legal destination reg to copy into. - unsigned NumElts = MVT::getVectorNumElements(VT); - MVT::ValueType EltTy = MVT::getVectorElementType(VT); + unsigned NumElts = VT.getVectorNumElements(); + MVT EltTy = VT.getVectorElementType(); unsigned NumVectorRegs = 1; @@ -366,24 +370,23 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, // Divide the input until we get to a supported size. This will always // end with a scalar if the target doesn't support vectors. - while (NumElts > 1 && - !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { + while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { NumElts >>= 1; NumVectorRegs <<= 1; } NumIntermediates = NumVectorRegs; - MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); + MVT NewVT = MVT::getVectorVT(EltTy, NumElts); if (!isTypeLegal(NewVT)) NewVT = EltTy; IntermediateVT = NewVT; - MVT::ValueType DestVT = getTypeToTransformTo(NewVT); + MVT DestVT = getTypeToTransformTo(NewVT); RegisterVT = DestVT; if (DestVT < NewVT) { // Value is expanded, e.g. i64 -> i16. - return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); + return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); } else { // Otherwise, promotion or legal types use the same number of registers as // the vector decimated to the appropriate level. @@ -425,7 +428,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, case ISD::XOR: if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) if (C->getAPIntValue().intersects(~Demanded)) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), DAG.getConstant(Demanded & C->getAPIntValue(), @@ -597,7 +600,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known if ((KnownOne & KnownOne2) == KnownOne) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), ANDC)); @@ -612,7 +615,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, // if we can expand it to have all bits set, do it if (Expanded.isAllOnesValue()) { if (Expanded != C->getAPIntValue()) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), TLO.DAG.getConstant(Expanded, VT)); return TLO.CombineTo(Op, New); @@ -688,7 +691,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, SDOperand NewSA = TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, InOp.getOperand(0), NewSA)); } @@ -705,9 +708,9 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, break; case ISD::SRL: if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); unsigned ShAmt = SA->getValue(); - unsigned VTSize = MVT::getSizeInBits(VT); + unsigned VTSize = VT.getSizeInBits(); SDOperand InOp = Op.getOperand(0); // If the shift count is an invalid immediate, don't do anything. @@ -749,7 +752,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, break; case ISD::SRA: if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); unsigned ShAmt = SA->getValue(); // If the shift count is an invalid immediate, don't do anything. @@ -762,7 +765,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, // demand the input sign bit. APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); if (HighBits.intersects(NewMask)) - InDemandedMask |= APInt::getSignBit(MVT::getSizeInBits(VT)); + InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, TLO, Depth+1)) @@ -785,22 +788,22 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, } break; case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); // Sign extension. Compute the demanded bits in the result that are not // present in the input. APInt NewBits = APInt::getHighBitsSet(BitWidth, - BitWidth - MVT::getSizeInBits(EVT)) & + BitWidth - EVT.getSizeInBits()) & NewMask; // If none of the extended bits are demanded, eliminate the sextinreg. if (NewBits == 0) return TLO.CombineTo(Op, Op.getOperand(0)); - APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT)); + APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); InSignBit.zext(BitWidth); APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, - MVT::getSizeInBits(EVT)) & + EVT.getSizeInBits()) & NewMask; // Since the sign extended bits are demanded, we know that the sign @@ -852,8 +855,8 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, break; } case ISD::SIGN_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); APInt NewBits = ~InMask & NewMask; @@ -948,9 +951,9 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, break; } case ISD::AssertZext: { - MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); APInt InMask = APInt::getLowBitsSet(BitWidth, - MVT::getSizeInBits(VT)); + VT.getSizeInBits()); if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, KnownZero, KnownOne, TLO, Depth+1)) return true; @@ -962,7 +965,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, #if 0 // If this is an FP->Int bitcast and if the sign bit is the only thing that // is demanded, turn this into a FGETSIGN. - if (NewMask == MVT::getIntVTSignBit(Op.getValueType()) && + if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && !MVT::isVector(Op.getOperand(0).getValueType())) { // Only do this xform if FGETSIGN is valid or if before legalize. @@ -972,7 +975,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, // place. We expect the SHL to be eliminated by other optimizations. SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), Op.getOperand(0)); - unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1; + unsigned ShVal = Op.getValueType().getSizeInBits()-1; SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), Sign, ShAmt)); @@ -1030,7 +1033,7 @@ unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, /// SimplifySetCC - Try to simplify a setcc built with the specified operands /// and cc. If it is unable to simplify it, return a null SDOperand. SDOperand -TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, +TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; @@ -1057,7 +1060,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, N0.getOperand(1).getOpcode() == ISD::Constant) { unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && - ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { + ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { if ((C1 == 0) == (Cond == ISD::SETEQ)) { // (srl (ctlz x), 5) == 0 -> X != 0 // (srl (ctlz x), 5) != 1 -> X != 0 @@ -1075,7 +1078,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, // If the LHS is a ZERO_EXTEND, perform the comparison on the input. if (N0.getOpcode() == ISD::ZERO_EXTEND) { - unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); + unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); // If the comparison constant has bits in the upper part, the // zero-extended value could never match. @@ -1118,10 +1121,10 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, } } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { - MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); - unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); - MVT::ValueType ExtDstTy = N0.getValueType(); - unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); + MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); + unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); + MVT ExtDstTy = N0.getValueType(); + unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); // If the extended part has any inconsistent bits, it cannot ever // compare equal. In other words, they have to be all ones or all @@ -1132,7 +1135,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, return DAG.getConstant(Cond == ISD::SETNE, VT); SDOperand ZextOp; - MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); + MVT Op0Ty = N0.getOperand(0).getValueType(); if (Op0Ty == ExtSrcTy) { ZextOp = N0.getOperand(0); } else { @@ -1161,7 +1164,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, // Invert the condition. ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); CC = ISD::getSetCCInverse(CC, - MVT::isInteger(N0.getOperand(0).getValueType())); + N0.getOperand(0).getValueType().isInteger()); return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); } @@ -1196,7 +1199,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, } APInt MinVal, MaxVal; - unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); + unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); if (ISD::isSignedIntSetCC(Cond)) { MinVal = APInt::getSignedMinValue(OperandBitSize); MaxVal = APInt::getSignedMaxValue(OperandBitSize); @@ -1313,7 +1316,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, if (N0 == N1) { // We can always fold X == X for integer setcc's. - if (MVT::isInteger(N0.getValueType())) + if (N0.getValueType().isInteger()) return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); unsigned UOF = ISD::getUnorderedFlavor(Cond); if (UOF == 2) // FP operators that are undefined on NaNs. @@ -1328,7 +1331,7 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, } if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && - MVT::isInteger(N0.getValueType())) { + N0.getValueType().isInteger()) { if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || N0.getOpcode() == ISD::XOR) { // Simplify (X+Y) == (X+Z) --> Y == Z @@ -1517,8 +1520,8 @@ bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, const MachineFrameInfo *MFI) const { if (LD->getOperand(0).Val != Base->getOperand(0).Val) return false; - MVT::ValueType VT = LD->getValueType(0); - if (MVT::getSizeInBits(VT) / 8 != Bytes) + MVT VT = LD->getValueType(0); + if (VT.getSizeInBits() / 8 != Bytes) return false; SDOperand Loc = LD->getOperand(1); @@ -1593,10 +1596,10 @@ TargetLowering::getConstraintType(const std::string &Constraint) const { /// LowerXConstraint - try to replace an X constraint, which matches anything, /// with another that has more specific requirements based on the type of the /// corresponding operand. -const char *TargetLowering::LowerXConstraint(MVT::ValueType ConstraintVT) const{ - if (MVT::isInteger(ConstraintVT)) +const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ + if (ConstraintVT.isInteger()) return "r"; - if (MVT::isFloatingPoint(ConstraintVT)) + if (ConstraintVT.isFloatingPoint()) return "f"; // works for many targets return 0; } @@ -1661,14 +1664,14 @@ void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, std::vector<unsigned> TargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { return std::vector<unsigned>(); } std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { if (Constraint[0] != '{') return std::pair<unsigned, const TargetRegisterClass*>(0, 0); assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); @@ -2039,7 +2042,7 @@ static mu magicu64(uint64_t d) /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, std::vector<SDNode*>* Created) const { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // Check to see if we can do this. if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) @@ -2080,7 +2083,7 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, } // Extract the sign bit and add it to the quotient SDOperand T = - DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, + DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, getShiftAmountTy())); if (Created) Created->push_back(T.Val); @@ -2093,7 +2096,7 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, std::vector<SDNode*>* Created) const { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // Check to see if we can do this. if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) |
