diff options
Diffstat (limited to 'llvm/lib/CodeGen')
20 files changed, 30 insertions, 40 deletions
diff --git a/llvm/lib/CodeGen/AllocationOrder.cpp b/llvm/lib/CodeGen/AllocationOrder.cpp index 40451c0d6c1..d840a2f69ab 100644 --- a/llvm/lib/CodeGen/AllocationOrder.cpp +++ b/llvm/lib/CodeGen/AllocationOrder.cpp @@ -48,7 +48,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, }); #ifndef NDEBUG for (unsigned I = 0, E = Hints.size(); I != E; ++I) - assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() && + assert(is_contained(Order, Hints[I]) && "Target hint is outside allocation order."); #endif } diff --git a/llvm/lib/CodeGen/AllocationOrder.h b/llvm/lib/CodeGen/AllocationOrder.h index 2aee3a63a2b..8223a52e333 100644 --- a/llvm/lib/CodeGen/AllocationOrder.h +++ b/llvm/lib/CodeGen/AllocationOrder.h @@ -18,6 +18,7 @@ #define LLVM_LIB_CODEGEN_ALLOCATIONORDER_H #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/MC/MCRegisterInfo.h" namespace llvm { @@ -79,9 +80,7 @@ public: bool isHint() const { return Pos <= 0; } /// Return true if PhysReg is a preferred register. - bool isHint(unsigned PhysReg) const { - return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end(); - } + bool isHint(unsigned PhysReg) const { return is_contained(Hints, PhysReg); } }; } // end namespace llvm diff --git a/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp b/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp index 480fca1454f..c64432b8141 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp @@ -83,7 +83,7 @@ static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, const auto &I = RegVars.find(RegNo); assert(RegNo != 0U && I != RegVars.end()); auto &VarSet = I->second; - const auto &VarPos = std::find(VarSet.begin(), VarSet.end(), Var); + const auto &VarPos = find(VarSet, Var); assert(VarPos != VarSet.end()); VarSet.erase(VarPos); // Don't keep empty sets in a map to keep it as small as possible. @@ -96,7 +96,7 @@ static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedVariable Var) { assert(RegNo != 0U); auto &VarSet = RegVars[RegNo]; - assert(std::find(VarSet.begin(), VarSet.end(), Var) == VarSet.end()); + assert(!is_contained(VarSet, Var)); VarSet.push_back(Var); } diff --git a/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp index c09ef6adea6..8baee4db772 100644 --- a/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp @@ -50,7 +50,7 @@ static void EmitCamlGlobal(const Module &M, AsmPrinter &AP, const char *Id) { std::string SymName; SymName += "caml"; size_t Letter = SymName.size(); - SymName.append(MId.begin(), std::find(MId.begin(), MId.end(), '.')); + SymName.append(MId.begin(), find(MId, '.')); SymName += "__"; SymName += Id; diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index ede404149a1..c87f3bc9073 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -3665,8 +3665,7 @@ isProfitableToFoldIntoAddressingMode(Instruction *I, ExtAddrMode &AMBefore, TPT.rollback(LastKnownGood); // If the match didn't cover I, then it won't be shared by it. - if (std::find(MatchedAddrModeInsts.begin(), MatchedAddrModeInsts.end(), - I) == MatchedAddrModeInsts.end()) + if (!is_contained(MatchedAddrModeInsts, I)) return false; MatchedAddrModeInsts.clear(); diff --git a/llvm/lib/CodeGen/LatencyPriorityQueue.cpp b/llvm/lib/CodeGen/LatencyPriorityQueue.cpp index 43218492ed1..86ef898932a 100644 --- a/llvm/lib/CodeGen/LatencyPriorityQueue.cpp +++ b/llvm/lib/CodeGen/LatencyPriorityQueue.cpp @@ -133,7 +133,7 @@ SUnit *LatencyPriorityQueue::pop() { void LatencyPriorityQueue::remove(SUnit *SU) { assert(!Queue.empty() && "Queue is empty!"); - std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(), SU); + std::vector<SUnit *>::iterator I = find(Queue, SU); if (I != std::prev(Queue.end())) std::swap(*I, Queue.back()); Queue.pop_back(); diff --git a/llvm/lib/CodeGen/LiveIntervalUnion.cpp b/llvm/lib/CodeGen/LiveIntervalUnion.cpp index 025d99ce788..fc2f233f6d6 100644 --- a/llvm/lib/CodeGen/LiveIntervalUnion.cpp +++ b/llvm/lib/CodeGen/LiveIntervalUnion.cpp @@ -14,6 +14,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/LiveIntervalUnion.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SparseBitVector.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -102,9 +103,7 @@ void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) { // Scan the vector of interfering virtual registers in this union. Assume it's // quite small. bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { - SmallVectorImpl<LiveInterval*>::const_iterator I = - std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg); - return I != InterferingVRegs.end(); + return is_contained(InterferingVRegs, VirtReg); } // Collect virtual registers in this union that interfere with this diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 689dd0764ce..2c2373f84ea 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -545,7 +545,7 @@ void MachineBasicBlock::addSuccessorWithoutProb(MachineBasicBlock *Succ) { void MachineBasicBlock::removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs) { - succ_iterator I = std::find(Successors.begin(), Successors.end(), Succ); + succ_iterator I = find(Successors, Succ); removeSuccessor(I, NormalizeSuccProbs); } @@ -611,7 +611,7 @@ void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) { } void MachineBasicBlock::removePredecessor(MachineBasicBlock *Pred) { - pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), Pred); + pred_iterator I = find(Predecessors, Pred); assert(I != Predecessors.end() && "Pred is not a predecessor of this block!"); Predecessors.erase(I); } @@ -775,7 +775,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, continue; unsigned Reg = OI->getReg(); - if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end()) + if (!is_contained(UsedRegs, Reg)) UsedRegs.push_back(Reg); } } @@ -802,9 +802,8 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(), E = Terminators.end(); I != E; ++I) { - if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) == - NewTerminators.end()) - Indexes->removeMachineInstrFromMaps(**I); + if (!is_contained(NewTerminators, *I)) + Indexes->removeMachineInstrFromMaps(**I); } } diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp index 27da8498897..d241e377336 100644 --- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp +++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp @@ -1166,8 +1166,7 @@ void MachineBlockPlacement::rotateLoop(BlockChain &LoopChain, } } - BlockChain::iterator ExitIt = - std::find(LoopChain.begin(), LoopChain.end(), ExitingBB); + BlockChain::iterator ExitIt = find(LoopChain, ExitingBB); if (ExitIt == LoopChain.end()) return; @@ -1190,7 +1189,7 @@ void MachineBlockPlacement::rotateLoop(BlockChain &LoopChain, void MachineBlockPlacement::rotateLoopWithProfile( BlockChain &LoopChain, MachineLoop &L, const BlockFilterSet &LoopBlockSet) { auto HeaderBB = L.getHeader(); - auto HeaderIter = std::find(LoopChain.begin(), LoopChain.end(), HeaderBB); + auto HeaderIter = find(LoopChain, HeaderBB); auto RotationPos = LoopChain.end(); BlockFrequency SmallestRotationCost = BlockFrequency::getMaxFrequency(); diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index 8fdf39d54bd..bf61ee04f9b 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -245,7 +245,7 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) { // Remember source that's copied to Def. Once it's clobbered, then // it's no longer available for copy propagation. RegList &DestList = SrcMap[Src]; - if (std::find(DestList.begin(), DestList.end(), Def) == DestList.end()) + if (!is_contained(DestList, Def)) DestList.push_back(Def); continue; diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp index 073fa90c76e..1f4acd01305 100644 --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -92,8 +92,7 @@ namespace { SmallVector<MachineBasicBlock*, 8> ExitBlocks; bool isExitBlock(const MachineBasicBlock *MBB) const { - return std::find(ExitBlocks.begin(), ExitBlocks.end(), MBB) != - ExitBlocks.end(); + return is_contained(ExitBlocks, MBB); } // Track 'estimated' register pressure. diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 6354c7c0872..5d2d88fa971 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1238,7 +1238,7 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) { if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) && MO->isKill()) { LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); - if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end()) + if (!is_contained(VI.Kills, MI)) report("Kill missing from LiveVariables", MO, MONum); } diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8870bcc3ebf..44be069a4d0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1571,8 +1571,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) { break; case ISD::TokenFactor: - if (Op.hasOneUse() && - std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { + if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) { // Queue up for processing. TFs.push_back(Op.getNode()); // Clean up in case the token factor is removed. diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index ee34f19bab7..87c968a85e9 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -599,8 +599,7 @@ void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI, unsigned FunctionLoweringInfo::findSwiftErrorVReg(const MachineBasicBlock *MBB, const Value* Val) const { // Find the index in SwiftErrorVals. - SwiftErrorValues::const_iterator I = - std::find(SwiftErrorVals.begin(), SwiftErrorVals.end(), Val); + SwiftErrorValues::const_iterator I = find(SwiftErrorVals, Val); assert(I != SwiftErrorVals.end() && "Can't find value in SwiftErrorVals"); return SwiftErrorMap.lookup(MBB)[I - SwiftErrorVals.begin()]; } @@ -608,8 +607,7 @@ unsigned FunctionLoweringInfo::findSwiftErrorVReg(const MachineBasicBlock *MBB, void FunctionLoweringInfo::setSwiftErrorVReg(const MachineBasicBlock *MBB, const Value* Val, unsigned VReg) { // Find the index in SwiftErrorVals. - SwiftErrorValues::iterator I = - std::find(SwiftErrorVals.begin(), SwiftErrorVals.end(), Val); + SwiftErrorValues::iterator I = find(SwiftErrorVals, Val); assert(I != SwiftErrorVals.end() && "Can't find value in SwiftErrorVals"); SwiftErrorMap[MBB][I - SwiftErrorVals.begin()] = VReg; } diff --git a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp index 1e5c4a73693..ded8e68fcbc 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp @@ -631,7 +631,7 @@ SUnit *ResourcePriorityQueue::pop() { void ResourcePriorityQueue::remove(SUnit *SU) { assert(!Queue.empty() && "Queue is empty!"); - std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(), SU); + std::vector<SUnit *>::iterator I = find(Queue, SU); if (I != std::prev(Queue.end())) std::swap(*I, Queue.back()); diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 802c459a022..3549ccd9e34 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1339,7 +1339,7 @@ void ScheduleDAGRRList::releaseInterferences(unsigned Reg) { LRegsMapT::iterator LRegsPos = LRegsMap.find(SU); if (Reg) { SmallVectorImpl<unsigned> &LRegs = LRegsPos->second; - if (std::find(LRegs.begin(), LRegs.end(), Reg) == LRegs.end()) + if (!is_contained(LRegs, Reg)) continue; } SU->isPending = false; @@ -1704,8 +1704,7 @@ public: void remove(SUnit *SU) override { assert(!Queue.empty() && "Queue is empty!"); assert(SU->NodeQueueId != 0 && "Not in queue!"); - std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(), - SU); + std::vector<SUnit *>::iterator I = find(Queue, SU); if (I != std::prev(Queue.end())) std::swap(*I, Queue.back()); Queue.pop_back(); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 23b1dc30a0d..642759afd01 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3388,7 +3388,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, SelectionDAG::DAGNodeDeletedListener NDL(*CurDAG, [&](SDNode *N, SDNode *E) { auto &Chain = ChainNodesMatched; - assert((!E || llvm::find(Chain, N) == Chain.end()) && + assert((!E || !is_contained(Chain, N)) && "Chain node replaced during MorphNode"); Chain.erase(std::remove(Chain.begin(), Chain.end(), N), Chain.end()); }); diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp index 029bd138f53..e9a5f14b04f 100644 --- a/llvm/lib/CodeGen/TailDuplicator.cpp +++ b/llvm/lib/CodeGen/TailDuplicator.cpp @@ -900,7 +900,7 @@ bool TailDuplicator::tailDuplicate(MachineFunction &MF, bool IsSimple, PE = Preds.end(); PI != PE; ++PI) { MachineBasicBlock *PredBB = *PI; - if (std::find(TDBBs.begin(), TDBBs.end(), PredBB) != TDBBs.end()) + if (is_contained(TDBBs, PredBB)) continue; // EH edges diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 8a3789a347c..78eb567daf8 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -467,7 +467,7 @@ static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI, for (unsigned i = StartIdx; i < MI.getNumOperands(); ++i) { MachineOperand &MO = MI.getOperand(i); - if (std::find(Ops.begin(), Ops.end(), i) != Ops.end()) { + if (is_contained(Ops, i)) { unsigned SpillSize; unsigned SpillOffset; // Compute the spill slot size and offset. diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index 17cd81c72e3..73e79b02163 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -354,7 +354,7 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, // Check that Phys is in the allocation order. We shouldn't heed hints // from VirtReg's register class if they aren't in the allocation order. The // target probably has a reason for removing the register. - if (std::find(Order.begin(), Order.end(), Phys) == Order.end()) + if (!is_contained(Order, Phys)) return; // All clear, tell the register allocator to prefer this register. |
