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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp16
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp2
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp16
3 files changed, 17 insertions, 17 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 87dffdcc932..eb44250cc05 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -112,7 +112,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize {
std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
/// PackedNodes - For nodes that need to be packed from MVT::Vector types to
- /// concrete packed types, this contains the mapping of ones we have already
+ /// concrete vector types, this contains the mapping of ones we have already
/// processed to the result.
std::map<SDOperand, SDOperand> PackedNodes;
@@ -1641,10 +1641,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
- // Turn this into a return of the packed type.
+ // Turn this into a return of the vector type.
Tmp2 = PackVectorOp(Tmp2, TVT);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
} else if (NumElems == 1) {
@@ -1793,10 +1793,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
- // Turn this into a normal store of the packed type.
+ // Turn this into a normal store of the vector type.
Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
ST->getSrcValueOffset());
@@ -2810,7 +2810,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the packed input.
@@ -3508,7 +3508,7 @@ SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
// Turn this into a packed extract_vector_elt operation.
@@ -5553,7 +5553,7 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the packed input.
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index d290d88615e..f6e9b2c88b4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -332,7 +332,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
if (Align == 0) {
Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
if (Align == 0) {
- // Alignment of packed types. FIXME!
+ // Alignment of vector types. FIXME!
Align = TM.getTargetData()->getTypeSize(Type);
Align = Log2_64(Align);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a156bda9750..38d2300d709 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -303,7 +303,7 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
// a <2 x int64> -> 4 x i32 registers.
unsigned NumVectorRegs = 1;
- // If this is a packed type, figure out what type it will decompose into
+ // If this is a vector type, figure out what type it will decompose into
// and how many of the elements it will use.
if (VT == MVT::Vector) {
const VectorType *PTy = cast<VectorType>(V->getType());
@@ -1861,7 +1861,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
SDOperand Op = getValue(I.getOperand(i));
- // If this is a vector type, force it to the right packed type.
+ // If this is a vector type, force it to the right vector type.
if (Op.getValueType() == MVT::Vector) {
const VectorType *OpTy = cast<VectorType>(I.getOperand(i)->getType());
MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
@@ -2970,7 +2970,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
const Type *EltTy = cast<VectorType>(I->getType())->getElementType();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
if (TVT != MVT::Other && isTypeLegal(TVT)) {
RetVals.push_back(TVT);
@@ -3036,7 +3036,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
const Type *EltTy = PTy->getElementType();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
if (TVT != MVT::Other && isTypeLegal(TVT)) {
SDOperand N = SDOperand(Result, i++);
@@ -3159,10 +3159,10 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
const Type *EltTy = PTy->getElementType();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
if (TVT != MVT::Other && isTypeLegal(TVT)) {
- // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
+ // Insert a VBIT_CONVERT of the MVT::Vector type to the vector type.
Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
Ops.push_back(Op);
Ops.push_back(DAG.getConstant(Flags, MVT::i32));
@@ -3205,7 +3205,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
const Type *EltTy = PTy->getElementType();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
if (TVT != MVT::Other && isTypeLegal(TVT)) {
RetTys.push_back(TVT);
@@ -3242,7 +3242,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
const Type *EltTy = cast<VectorType>(RetTy)->getElementType();
// Figure out if there is a Packed type corresponding to this Vector
- // type. If so, convert to the packed type.
+ // type. If so, convert to the vector type.
MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),NumElems);
if (TVT != MVT::Other && isTypeLegal(TVT)) {
// Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
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