diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 17 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 10 |
3 files changed, 22 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 225d2b39dfa..9cdbb910303 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -4773,6 +4773,11 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, assert(0 && "Cast from unsupported vector type not implemented yet!"); } } + case ISD::VSELECT: + Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), + PackVectorOp(Op.getOperand(1), NewVT), + PackVectorOp(Op.getOperand(2), NewVT)); + break; } if (TLI.isTypeLegal(NewVT)) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index a2b575ff31d..b58b67ed534 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2760,15 +2760,16 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const { case ISD::SETCC: return "setcc"; case ISD::SELECT: return "select"; case ISD::SELECT_CC: return "select_cc"; - case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; - case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt"; - case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; + case ISD::VSELECT: return "vselect"; + case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; + case ISD::VINSERT_VECTOR_ELT: return "vinsert_vector_elt"; + case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; case ISD::VEXTRACT_VECTOR_ELT: return "vextract_vector_elt"; - case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; - case ISD::VBUILD_VECTOR: return "vbuild_vector"; - case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; - case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle"; - case ISD::VBIT_CONVERT: return "vbit_convert"; + case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; + case ISD::VBUILD_VECTOR: return "vbuild_vector"; + case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; + case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle"; + case ISD::VBIT_CONVERT: return "vbit_convert"; case ISD::ADDC: return "addc"; case ISD::ADDE: return "adde"; case ISD::SUBC: return "subc"; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index dba4c736b70..c02654175e1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -992,8 +992,14 @@ void SelectionDAGLowering::visitSelect(User &I) { SDOperand Cond = getValue(I.getOperand(0)); SDOperand TrueVal = getValue(I.getOperand(1)); SDOperand FalseVal = getValue(I.getOperand(2)); - setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, - TrueVal, FalseVal)); + if (!isa<PackedType>(I.getType())) { + setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, + TrueVal, FalseVal)); + } else { + setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal, + *(TrueVal.Val->op_end()-2), + *(TrueVal.Val->op_end()-1))); + } } void SelectionDAGLowering::visitCast(User &I) { |
