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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp8
1 files changed, 1 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5a6077a3ca1..0e719f844e9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1102,14 +1102,8 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) {
}
// fold (sub x, x) -> 0
- if (N0 == N1) {
- if (AfterLegalize && ISD::isBuildVectorAllZeros(N0.Val))
- // For example, zero vectors might be normalized to a particular vector
- // type to ensure they are CSE'd. Avoid issuing zero vector nodes of
- // *unexpected* type after legalization.
- return N0;
+ if (N0 == N1)
return DAG.getConstant(0, N->getValueType(0));
- }
// fold (sub c1, c2) -> c1-c2
if (N0C && N1C)
return DAG.getNode(ISD::SUB, VT, N0, N1);
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