summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp19
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 6e829a35f7c..f1526a4ae46 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1479,6 +1479,25 @@ bool TargetLowering::SimplifyDemandedVectorElts(
KnownZero.insertBits(SubZero, SubIdx);
break;
}
+ case ISD::EXTRACT_SUBVECTOR: {
+ if (!isa<ConstantSDNode>(Op.getOperand(1)))
+ break;
+ SDValue Src = Op.getOperand(0);
+ unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
+ const APInt& Idx = cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue();
+ if (Idx.uge(NumSrcElts - NumElts))
+ break;
+ // Offset the demanded elts by the subvector index.
+ uint64_t SubIdx = Idx.getZExtValue();
+ APInt SrcElts = DemandedElts.zext(NumSrcElts).shl(SubIdx);
+ APInt SrcUndef, SrcZero;
+ if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO,
+ Depth + 1))
+ return true;
+ KnownUndef = SrcUndef.extractBits(NumElts, SubIdx);
+ KnownZero = SrcZero.extractBits(NumElts, SubIdx);
+ break;
+ }
case ISD::INSERT_VECTOR_ELT: {
SDValue Vec = Op.getOperand(0);
SDValue Scl = Op.getOperand(1);
OpenPOWER on IntegriCloud