1 files changed, 1 insertions, 21 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 09b5f3c010b..a17caa1469a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -292,19 +292,7 @@ public:
       FuncInfo.ValueMap.find(V);
     assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
 
-    MVT::ValueType RegVT = VT;
-    if (TLI.getTypeAction(VT) == 1)          // Must promote this value?
-      RegVT = TLI.getTypeToTransformTo(VT);
-
-    N = DAG.getCopyFromReg(VMI->second, RegVT, DAG.getEntryNode());
-
-    if (RegVT != VT)
-      if (MVT::isFloatingPoint(VT))
-        N = DAG.getNode(ISD::FP_ROUND, VT, N);
-      else
-        N = DAG.getNode(ISD::TRUNCATE, VT, N);
-
-    return N;
+    return N = DAG.getCopyFromReg(VMI->second, VT, DAG.getEntryNode());
   }
 
   const SDOperand &setValue(const Value *V, SDOperand NewN) {
@@ -843,14 +831,6 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
   assert((Op.getOpcode() != ISD::CopyFromReg ||
           cast<RegSDNode>(Op)->getReg() != Reg) &&
          "Copy from a reg to the same reg!");
-  MVT::ValueType VT = Op.getValueType();
-  if (TLI.getTypeAction(VT) == 1) {       // Must promote this value?
-    if (MVT::isFloatingPoint(VT))
-      Op = DAG.getNode(ISD::FP_EXTEND, TLI.getTypeToTransformTo(VT), Op);
-    else
-      Op = DAG.getNode(ISD::ZERO_EXTEND, TLI.getTypeToTransformTo(VT), Op);
-  }
-
   return DAG.getCopyToReg(SDL.getRoot(), Op, Reg);
 }