1 files changed, 38 insertions, 18 deletions

diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.h b/llvm/lib/CodeGen/ScheduleDAGInstrs.h
index a27a8c4891a..7830f83fff5 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.h
@@ -101,6 +101,7 @@ namespace llvm {
   /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
   /// MachineInstrs.
   class LLVM_LIBRARY_VISIBILITY ScheduleDAGInstrs : public ScheduleDAG {
+  protected:
     const MachineLoopInfo &MLI;
     const MachineDominatorTree &MDT;
     const MachineFrameInfo *MFI;
@@ -112,6 +113,23 @@ namespace llvm {
     /// Live Intervals provides reaching defs in preRA scheduling.
     LiveIntervals *LIS;
 
+    /// State specific to the current scheduling region.
+    ///
+
+    // The block in which to insert instructions
+    MachineBasicBlock *BB;
+
+    // The beginning of the range to
+    // be scheduled. The range extends
+    // to InsertPos.
+    MachineBasicBlock::iterator Begin;
+
+    // The position to insert instructions
+    MachineBasicBlock::iterator InsertPos;
+
+    // The index in BB of InsertPos.
+    unsigned InsertPosIndex;
+
     /// After calling BuildSchedGraph, each machine instruction in the current
     /// scheduling region is mapped to an SUnit.
     DenseMap<MachineInstr*, SUnit*> MISUnitMap;
@@ -209,11 +227,6 @@ namespace llvm {
     MachineInstr *FirstDbgValue;
 
   public:
-    MachineBasicBlock::iterator Begin;    // The beginning of the range to
-                                          // be scheduled. The range extends
-                                          // to InsertPos.
-    unsigned InsertPosIndex;              // The index in BB of InsertPos.
-
     explicit ScheduleDAGInstrs(MachineFunction &mf,
                                const MachineLoopInfo &mli,
                                const MachineDominatorTree &mdt,
@@ -222,6 +235,12 @@ namespace llvm {
 
     virtual ~ScheduleDAGInstrs() {}
 
+    /// begin - Return an iterator to the top of the current scheduling region.
+    MachineBasicBlock::iterator begin() const { return Begin; }
+
+    /// end - Return an iterator to the bottom of the current scheduling region.
+    MachineBasicBlock::iterator end() const { return InsertPos; }
+
     /// NewSUnit - Creates a new SUnit and return a ptr to it.
     ///
     SUnit *NewSUnit(MachineInstr *MI) {
@@ -235,13 +254,22 @@ namespace llvm {
       return &SUnits.back();
     }
 
+    /// StartBlock - Prepare to perform scheduling in the given block.
+    ///
+    virtual void StartBlock(MachineBasicBlock *BB);
 
-    /// Run - perform scheduling.
+    /// FinishBlock - Clean up after scheduling in the given block.
     ///
-    void Run(MachineBasicBlock *bb,
-             MachineBasicBlock::iterator begin,
-             MachineBasicBlock::iterator end,
-             unsigned endindex);
+    virtual void FinishBlock();
+
+    /// Initialize the scheduler state for the next scheduling region.
+    virtual void enterRegion(MachineBasicBlock *bb,
+                             MachineBasicBlock::iterator begin,
+                             MachineBasicBlock::iterator end,
+                             unsigned endcount);
+
+    /// Notify that the scheduler has finished scheduling the current region.
+    virtual void exitRegion();
 
     /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
     /// input.
@@ -266,19 +294,11 @@ namespace llvm {
     virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
                                        SDep& dep) const;
 
-    /// StartBlock - Prepare to perform scheduling in the given block.
-    ///
-    virtual void StartBlock(MachineBasicBlock *BB);
-
     /// Schedule - Order nodes according to selected style, filling
     /// in the Sequence member.
     ///
     virtual void Schedule() = 0;
 
-    /// FinishBlock - Clean up after scheduling in the given block.
-    ///
-    virtual void FinishBlock();
-
     virtual void dumpNode(const SUnit *SU) const;
 
     /// Return a label for a DAG node that points to an instruction.