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-rw-r--r--llvm/lib/CodeGen/ScheduleDAGInstrs.cpp25
1 files changed, 13 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 510716e8a77..e2cb56cc852 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -398,7 +398,7 @@ LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
// No point in tracking lanemasks if we don't have interesting subregisters.
const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
if (!RC.HasDisjunctSubRegs)
- return ~0u;
+ return LaneBitmask::getAll();
unsigned SubReg = MO.getSubReg();
if (SubReg == 0)
@@ -424,14 +424,14 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
DefLaneMask = getLaneMaskForMO(MO);
// If we have a <read-undef> flag, none of the lane values comes from an
// earlier instruction.
- KillLaneMask = IsKill ? ~0u : DefLaneMask;
+ KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask;
// Clear undef flag, we'll re-add it later once we know which subregister
// Def is first.
MO.setIsUndef(false);
} else {
- DefLaneMask = ~0u;
- KillLaneMask = ~0u;
+ DefLaneMask = LaneBitmask::getAll();
+ KillLaneMask = LaneBitmask::getAll();
}
if (MO.isDead()) {
@@ -444,12 +444,12 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
E = CurrentVRegUses.end(); I != E; /*empty*/) {
LaneBitmask LaneMask = I->LaneMask;
// Ignore uses of other lanes.
- if ((LaneMask & KillLaneMask) == 0) {
+ if ((LaneMask & KillLaneMask).none()) {
++I;
continue;
}
- if ((LaneMask & DefLaneMask) != 0) {
+ if (!(LaneMask & DefLaneMask).none()) {
SUnit *UseSU = I->SU;
MachineInstr *Use = UseSU->getInstr();
SDep Dep(SU, SDep::Data, Reg);
@@ -461,7 +461,7 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
LaneMask &= ~KillLaneMask;
// If we found a Def for all lanes of this use, remove it from the list.
- if (LaneMask != 0) {
+ if (!LaneMask.none()) {
I->LaneMask = LaneMask;
++I;
} else
@@ -484,7 +484,7 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
CurrentVRegDefs.end())) {
// Ignore defs for other lanes.
- if ((V2SU.LaneMask & LaneMask) == 0)
+ if ((V2SU.LaneMask & LaneMask).none())
continue;
// Add an output dependence.
SUnit *DefSU = V2SU.SU;
@@ -507,11 +507,11 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
V2SU.SU = SU;
V2SU.LaneMask = OverlapMask;
- if (NonOverlapMask != 0)
+ if (!NonOverlapMask.none())
CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));
}
// If there was no CurrentVRegDefs entry for some lanes yet, create one.
- if (LaneMask != 0)
+ if (!LaneMask.none())
CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
}
@@ -527,7 +527,8 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
unsigned Reg = MO.getReg();
// Remember the use. Data dependencies will be added when we find the def.
- LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO) : ~0u;
+ LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO)
+ : LaneBitmask::getAll();
CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
// Add antidependences to the following defs of the vreg.
@@ -535,7 +536,7 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
CurrentVRegDefs.end())) {
// Ignore defs for unrelated lanes.
LaneBitmask PrevDefLaneMask = V2SU.LaneMask;
- if ((PrevDefLaneMask & LaneMask) == 0)
+ if ((PrevDefLaneMask & LaneMask).none())
continue;
if (V2SU.SU == SU)
continue;
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