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-rw-r--r--llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp77
1 files changed, 45 insertions, 32 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 57b97f87f2d..6fa77fa92be 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -131,7 +131,8 @@ MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
return *MBB;
}
-bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U) {
+bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
+ MachineIRBuilder &MIRBuilder) {
// FIXME: handle signed/unsigned wrapping flags.
// Get or create a virtual register for each value.
@@ -145,7 +146,8 @@ bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U) {
return true;
}
-bool IRTranslator::translateCompare(const User &U) {
+bool IRTranslator::translateCompare(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const CmpInst *CI = dyn_cast<CmpInst>(&U);
unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
@@ -162,7 +164,7 @@ bool IRTranslator::translateCompare(const User &U) {
return true;
}
-bool IRTranslator::translateRet(const User &U) {
+bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
const ReturnInst &RI = cast<ReturnInst>(U);
const Value *Ret = RI.getReturnValue();
// The target may mess up with the insertion point, but
@@ -171,7 +173,7 @@ bool IRTranslator::translateRet(const User &U) {
return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
}
-bool IRTranslator::translateBr(const User &U) {
+bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
const BranchInst &BrInst = cast<BranchInst>(U);
unsigned Succ = 0;
if (!BrInst.isUnconditional()) {
@@ -193,7 +195,7 @@ bool IRTranslator::translateBr(const User &U) {
return true;
}
-bool IRTranslator::translateLoad(const User &U) {
+bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
const LoadInst &LI = cast<LoadInst>(U);
if (!TPC->isGlobalISelAbortEnabled() && LI.isAtomic())
@@ -215,7 +217,7 @@ bool IRTranslator::translateLoad(const User &U) {
return true;
}
-bool IRTranslator::translateStore(const User &U) {
+bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
const StoreInst &SI = cast<StoreInst>(U);
if (!TPC->isGlobalISelAbortEnabled() && SI.isAtomic())
@@ -240,7 +242,8 @@ bool IRTranslator::translateStore(const User &U) {
return true;
}
-bool IRTranslator::translateExtractValue(const User &U) {
+bool IRTranslator::translateExtractValue(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const Value *Src = U.getOperand(0);
Type *Int32Ty = Type::getInt32Ty(U.getContext());
SmallVector<Value *, 1> Indices;
@@ -265,7 +268,8 @@ bool IRTranslator::translateExtractValue(const User &U) {
return true;
}
-bool IRTranslator::translateInsertValue(const User &U) {
+bool IRTranslator::translateInsertValue(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const Value *Src = U.getOperand(0);
Type *Int32Ty = Type::getInt32Ty(U.getContext());
SmallVector<Value *, 1> Indices;
@@ -292,14 +296,16 @@ bool IRTranslator::translateInsertValue(const User &U) {
return true;
}
-bool IRTranslator::translateSelect(const User &U) {
+bool IRTranslator::translateSelect(const User &U,
+ MachineIRBuilder &MIRBuilder) {
MIRBuilder.buildSelect(getOrCreateVReg(U), getOrCreateVReg(*U.getOperand(0)),
getOrCreateVReg(*U.getOperand(1)),
getOrCreateVReg(*U.getOperand(2)));
return true;
}
-bool IRTranslator::translateBitCast(const User &U) {
+bool IRTranslator::translateBitCast(const User &U,
+ MachineIRBuilder &MIRBuilder) {
if (LLT{*U.getOperand(0)->getType(), *DL} == LLT{*U.getType(), *DL}) {
unsigned &Reg = ValToVReg[&U];
if (Reg)
@@ -308,17 +314,19 @@ bool IRTranslator::translateBitCast(const User &U) {
Reg = getOrCreateVReg(*U.getOperand(0));
return true;
}
- return translateCast(TargetOpcode::G_BITCAST, U);
+ return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
}
-bool IRTranslator::translateCast(unsigned Opcode, const User &U) {
+bool IRTranslator::translateCast(unsigned Opcode, const User &U,
+ MachineIRBuilder &MIRBuilder) {
unsigned Op = getOrCreateVReg(*U.getOperand(0));
unsigned Res = getOrCreateVReg(U);
MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
return true;
}
-bool IRTranslator::translateGetElementPtr(const User &U) {
+bool IRTranslator::translateGetElementPtr(const User &U,
+ MachineIRBuilder &MIRBuilder) {
// FIXME: support vector GEPs.
if (U.getType()->isVectorTy())
return false;
@@ -388,7 +396,8 @@ bool IRTranslator::translateGetElementPtr(const User &U) {
return true;
}
-bool IRTranslator::translateMemcpy(const CallInst &CI) {
+bool IRTranslator::translateMemcpy(const CallInst &CI,
+ MachineIRBuilder &MIRBuilder) {
LLT SizeTy{*CI.getArgOperand(2)->getType(), *DL};
if (cast<PointerType>(CI.getArgOperand(0)->getType())->getAddressSpace() !=
0 ||
@@ -409,7 +418,8 @@ bool IRTranslator::translateMemcpy(const CallInst &CI) {
CallLowering::ArgInfo(0, CI.getType()), Args);
}
-void IRTranslator::getStackGuard(unsigned DstReg) {
+void IRTranslator::getStackGuard(unsigned DstReg,
+ MachineIRBuilder &MIRBuilder) {
auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
MIB.addDef(DstReg);
@@ -428,8 +438,8 @@ void IRTranslator::getStackGuard(unsigned DstReg) {
MIB.setMemRefs(MemRefs, MemRefs + 1);
}
-bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
- Intrinsic::ID ID) {
+bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
+ MachineIRBuilder &MIRBuilder) {
unsigned Op = 0;
switch (ID) {
default: return false;
@@ -440,7 +450,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
case Intrinsic::umul_with_overflow: Op = TargetOpcode::G_UMULO; break;
case Intrinsic::smul_with_overflow: Op = TargetOpcode::G_SMULO; break;
case Intrinsic::memcpy:
- return translateMemcpy(CI);
+ return translateMemcpy(CI, MIRBuilder);
case Intrinsic::eh_typeid_for: {
GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
unsigned Reg = getOrCreateVReg(CI);
@@ -456,12 +466,12 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
return true;
}
case Intrinsic::stackguard:
- getStackGuard(getOrCreateVReg(CI));
+ getStackGuard(getOrCreateVReg(CI), MIRBuilder);
return true;
case Intrinsic::stackprotector: {
LLT PtrTy{*CI.getArgOperand(0)->getType(), *DL};
unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
- getStackGuard(GuardVal);
+ getStackGuard(GuardVal, MIRBuilder);
AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
MIRBuilder.buildStore(
@@ -496,7 +506,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
return true;
}
-bool IRTranslator::translateCall(const User &U) {
+bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
const CallInst &CI = cast<CallInst>(U);
auto TII = MF->getTarget().getIntrinsicInfo();
const Function *F = CI.getCalledFunction();
@@ -518,7 +528,7 @@ bool IRTranslator::translateCall(const User &U) {
assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
- if (translateKnownIntrinsic(CI, ID))
+ if (translateKnownIntrinsic(CI, ID, MIRBuilder))
return true;
unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
@@ -534,7 +544,8 @@ bool IRTranslator::translateCall(const User &U) {
return true;
}
-bool IRTranslator::translateInvoke(const User &U) {
+bool IRTranslator::translateInvoke(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const InvokeInst &I = cast<InvokeInst>(U);
MCContext &Context = MF->getContext();
@@ -586,7 +597,8 @@ bool IRTranslator::translateInvoke(const User &U) {
return true;
}
-bool IRTranslator::translateLandingPad(const User &U) {
+bool IRTranslator::translateLandingPad(const User &U,
+ MachineIRBuilder &MIRBuilder) {
const LandingPadInst &LP = cast<LandingPadInst>(U);
MachineBasicBlock &MBB = MIRBuilder.getMBB();
@@ -636,7 +648,8 @@ bool IRTranslator::translateLandingPad(const User &U) {
return true;
}
-bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
+bool IRTranslator::translateStaticAlloca(const AllocaInst &AI,
+ MachineIRBuilder &MIRBuilder) {
if (!TPC->isGlobalISelAbortEnabled() && !AI.isStaticAlloca())
return false;
@@ -647,7 +660,7 @@ bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
return true;
}
-bool IRTranslator::translatePHI(const User &U) {
+bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
const PHINode &PI = cast<PHINode>(U);
auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
MIB.addDef(getOrCreateVReg(PI));
@@ -659,7 +672,7 @@ bool IRTranslator::translatePHI(const User &U) {
void IRTranslator::finishPendingPhis() {
for (std::pair<const PHINode *, MachineInstr *> &Phi : PendingPHIs) {
const PHINode *PI = Phi.first;
- MachineInstrBuilder MIB(MIRBuilder.getMF(), Phi.second);
+ MachineInstrBuilder MIB(*MF, Phi.second);
// All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
// won't create extra control flow here, otherwise we need to find the
@@ -675,10 +688,10 @@ void IRTranslator::finishPendingPhis() {
}
bool IRTranslator::translate(const Instruction &Inst) {
- MIRBuilder.setDebugLoc(Inst.getDebugLoc());
+ CurBuilder.setDebugLoc(Inst.getDebugLoc());
switch(Inst.getOpcode()) {
#define HANDLE_INST(NUM, OPCODE, CLASS) \
- case Instruction::OPCODE: return translate##OPCODE(Inst);
+ case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
#include "llvm/IR/Instruction.def"
default:
if (!TPC->isGlobalISelAbortEnabled())
@@ -701,7 +714,7 @@ bool IRTranslator::translate(const Constant &C, unsigned Reg) {
else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
switch(CE->getOpcode()) {
#define HANDLE_INST(NUM, OPCODE, CLASS) \
- case Instruction::OPCODE: return translate##OPCODE(*CE);
+ case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
#include "llvm/IR/Instruction.def"
default:
if (!TPC->isGlobalISelAbortEnabled())
@@ -731,7 +744,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
if (F.empty())
return false;
CLI = MF->getSubtarget().getCallLowering();
- MIRBuilder.setMF(*MF);
+ CurBuilder.setMF(*MF);
EntryBuilder.setMF(*MF);
MRI = &MF->getRegInfo();
DL = &F.getParent()->getDataLayout();
@@ -766,7 +779,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
MachineBasicBlock &MBB = getOrCreateBB(BB);
// Set the insertion point of all the following translations to
// the end of this basic block.
- MIRBuilder.setMBB(MBB);
+ CurBuilder.setMBB(MBB);
for (const Instruction &Inst: BB) {
Succeeded &= translate(Inst);
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