diff options
Diffstat (limited to 'lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp')
| -rw-r--r-- | lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp index 86f5cefe03d..46252b99de3 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp +++ b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp @@ -36,11 +36,9 @@ using namespace lldb_private; #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC) -//---------------------------------------------------------------------- // // ITSession implementation // -//---------------------------------------------------------------------- static bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo ®_info) { ::memset(®_info, 0, sizeof(RegisterInfo)); @@ -709,11 +707,9 @@ uint32_t ITSession::GetCond() { #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD) #define VFPv2v3 (VFPv2 | VFPv3) -//---------------------------------------------------------------------- // // EmulateInstructionARM implementation // -//---------------------------------------------------------------------- void EmulateInstructionARM::Initialize() { PluginManager::RegisterPlugin(GetPluginNameStatic(), @@ -12852,9 +12848,7 @@ EmulateInstructionARM::ARMOpcode * EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, uint32_t arm_isa) { static ARMOpcode g_arm_opcodes[] = { - //---------------------------------------------------------------------- // Prologue instructions - //---------------------------------------------------------------------- // push register(s) {0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, @@ -12893,9 +12887,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, {0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, - //---------------------------------------------------------------------- // Epilogue instructions - //---------------------------------------------------------------------- {0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop <registers>"}, @@ -12906,15 +12898,11 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, {0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, - //---------------------------------------------------------------------- // Supervisor Call (previously Software Interrupt) - //---------------------------------------------------------------------- {0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSVC, "svc #imm24"}, - //---------------------------------------------------------------------- // Branch instructions - //---------------------------------------------------------------------- // To resolve ambiguity, "blx <label>" should come before "b #imm24" and // "bl <label>". {0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, No_VFP, eSize32, @@ -12932,9 +12920,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, {0x0ffffff0, 0x012fff20, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"}, - //---------------------------------------------------------------------- // Data-processing instructions - //---------------------------------------------------------------------- // adc (immediate) {0x0fe00000, 0x02a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"}, @@ -13098,9 +13084,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,<Rn>,<Rm{,<shift>}"}, - //---------------------------------------------------------------------- // Load instructions - //---------------------------------------------------------------------- {0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>"}, {0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, No_VFP, eSize32, @@ -13165,9 +13149,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"}, - //---------------------------------------------------------------------- // Store instructions - //---------------------------------------------------------------------- {0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>"}, {0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, No_VFP, eSize32, @@ -13211,9 +13193,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"}, - //---------------------------------------------------------------------- // Other instructions - //---------------------------------------------------------------------- {0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}"}, {0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, @@ -13241,9 +13221,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, uint32_t arm_isa) { static ARMOpcode g_thumb_opcodes[] = { - //---------------------------------------------------------------------- // Prologue instructions - //---------------------------------------------------------------------- // push register(s) {0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, No_VFP, eSize16, @@ -13287,9 +13265,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, {0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"}, - //---------------------------------------------------------------------- // Epilogue instructions - //---------------------------------------------------------------------- {0xfffff800, 0x0000a800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"}, @@ -13306,15 +13282,11 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, {0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"}, - //---------------------------------------------------------------------- // Supervisor Call (previously Software Interrupt) - //---------------------------------------------------------------------- {0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSVC, "svc #imm8"}, - //---------------------------------------------------------------------- // If Then makes up to four following instructions conditional. - //---------------------------------------------------------------------- // The next 5 opcode _must_ come before the if then instruction {0xffffffff, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop"}, @@ -13329,9 +13301,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, {0xffffff00, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"}, - //---------------------------------------------------------------------- // Branch instructions - //---------------------------------------------------------------------- // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8". {0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"}, @@ -13366,9 +13336,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, {0xfff0fff0, 0xe8d0f010, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"}, - //---------------------------------------------------------------------- // Data-processing instructions - //---------------------------------------------------------------------- // adc (immediate) {0xfbe08000, 0xf1400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"}, @@ -13596,20 +13564,16 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, {0xffffff00, 0xf3de8f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "SUBS<c> PC, LR, #<imm8>"}, - //---------------------------------------------------------------------- // RFE instructions *** IMPORTANT *** THESE MUST BE LISTED **BEFORE** THE // LDM.. Instructions in this table; // otherwise the wrong instructions will be selected. - //---------------------------------------------------------------------- {0xffd0ffff, 0xe810c000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfedb<c> <Rn>{!}"}, {0xffd0ffff, 0xe990c000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{ia}<c> <Rn>{!}"}, - //---------------------------------------------------------------------- // Load instructions - //---------------------------------------------------------------------- {0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>"}, {0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, @@ -13717,9 +13681,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"}, - //---------------------------------------------------------------------- // Store instructions - //---------------------------------------------------------------------- {0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>"}, {0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, @@ -13776,9 +13738,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"}, - //---------------------------------------------------------------------- // Other instructions - //---------------------------------------------------------------------- {0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>"}, {0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, No_VFP, eSize32, |
