diff options
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/python_api/lldbutil')
| -rw-r--r-- | lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py b/lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py index 49a78888ad8..a19cc5c375f 100644 --- a/lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py +++ b/lldb/packages/Python/lldbsuite/test/python_api/lldbutil/iter/TestRegistersIterator.py @@ -76,17 +76,18 @@ class RegistersIteratorTestCase(TestBase): REGs = lldbutil.get_ESRs(frame) if self.platformIsDarwin(): - num = len(REGs) - if self.TraceOn(): - print( - "\nNumber of exception state registers: %d" % - num) - for reg in REGs: - self.assertTrue(reg) + if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k': + num = len(REGs) if self.TraceOn(): print( - "%s => %s" % - (reg.GetName(), reg.GetValue())) + "\nNumber of exception state registers: %d" % + num) + for reg in REGs: + self.assertTrue(reg) + if self.TraceOn(): + print( + "%s => %s" % + (reg.GetName(), reg.GetValue())) else: self.assertIsNone(REGs) @@ -99,7 +100,8 @@ class RegistersIteratorTestCase(TestBase): REGs = lldbutil.get_registers( frame, "Exception State Registers") if self.platformIsDarwin(): - self.assertIsNotNone(REGs) + if self.getArchitecture() != 'armv7' and self.getArchitecture() != 'armv7k': + self.assertIsNotNone(REGs) else: self.assertIsNone(REGs) |
