diff options
Diffstat (limited to 'compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cc')
| -rw-r--r-- | compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cc | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cc b/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cc index e39160b9bb3..a2f7ff4217f 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cc +++ b/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cc @@ -250,8 +250,7 @@ static T AtomicLoad(ThreadState *thr, uptr pc, const volatile T *a, // This fast-path is critical for performance. // Assume the access is atomic. if (!IsAcquireOrder(mo) && sizeof(T) <= sizeof(a)) { - if (flags()->report_atomic_races) - MemoryReadAtomic(thr, pc, (uptr)a, SizeLog<T>()); + MemoryReadAtomic(thr, pc, (uptr)a, SizeLog<T>()); return *a; } SyncVar *s = CTX()->synctab.GetOrCreateAndLock(thr, pc, (uptr)a, false); @@ -260,8 +259,7 @@ static T AtomicLoad(ThreadState *thr, uptr pc, const volatile T *a, T v = *a; s->mtx.ReadUnlock(); __sync_synchronize(); - if (flags()->report_atomic_races) - MemoryReadAtomic(thr, pc, (uptr)a, SizeLog<T>()); + MemoryReadAtomic(thr, pc, (uptr)a, SizeLog<T>()); return v; } @@ -269,8 +267,7 @@ template<typename T> static void AtomicStore(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) { CHECK(IsStoreOrder(mo)); - if (flags()->report_atomic_races) - MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>()); + MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>()); // This fast-path is critical for performance. // Assume the access is atomic. // Strictly saying even relaxed store cuts off release sequence, @@ -292,8 +289,7 @@ static void AtomicStore(ThreadState *thr, uptr pc, volatile T *a, T v, template<typename T, T (*F)(volatile T *v, T op)> static T AtomicRMW(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) { - if (flags()->report_atomic_races) - MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>()); + MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>()); SyncVar *s = CTX()->synctab.GetOrCreateAndLock(thr, pc, (uptr)a, true); thr->clock.set(thr->tid, thr->fast_state.epoch()); if (IsAcqRelOrder(mo)) @@ -353,8 +349,7 @@ template<typename T> static bool AtomicCAS(ThreadState *thr, uptr pc, volatile T *a, T *c, T v, morder mo, morder fmo) { (void)fmo; // Unused because llvm does not pass it yet. - if (flags()->report_atomic_races) - MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>()); + MemoryWriteAtomic(thr, pc, (uptr)a, SizeLog<T>()); SyncVar *s = CTX()->synctab.GetOrCreateAndLock(thr, pc, (uptr)a, true); thr->clock.set(thr->tid, thr->fast_state.epoch()); if (IsAcqRelOrder(mo)) |
