diff options
Diffstat (limited to 'clang/test/OpenMP/simd_codegen.cpp')
| -rw-r--r-- | clang/test/OpenMP/simd_codegen.cpp | 33 |
1 files changed, 30 insertions, 3 deletions
diff --git a/clang/test/OpenMP/simd_codegen.cpp b/clang/test/OpenMP/simd_codegen.cpp index 0a5b38a0ce3..4bd06a7fdf2 100644 --- a/clang/test/OpenMP/simd_codegen.cpp +++ b/clang/test/OpenMP/simd_codegen.cpp @@ -185,9 +185,6 @@ void simple(float *a, float *b, float *c, float *d) { // CHECK: store i32 -1, i32* [[A:%.+]], A = -1; #pragma omp simd lastprivate(A) -// Clause 'lastprivate' implementation is not completed yet. -// Test checks that one iteration is separated in presence of lastprivate. -// // CHECK: store i64 0, i64* [[OMP_IV7:%[^,]+]] // CHECK: br label %[[SIMD_LOOP7_COND:[^,]+]] // CHECK: [[SIMD_LOOP7_COND]] @@ -212,6 +209,36 @@ void simple(float *a, float *b, float *c, float *d) { // CHECK: [[SIMPLE_LOOP7_END]] // CHECK-NEXT: [[A_PRIV_VAL:%.+]] = load i32, i32* [[A_PRIV]], // CHECK-NEXT: store i32 [[A_PRIV_VAL]], i32* [[A]], + int R; + // CHECK: store i32 -1, i32* [[R:%.+]], + R = -1; +// CHECK: store i64 0, i64* [[OMP_IV8:%[^,]+]] +// CHECK: store i32 1, i32* [[R_PRIV:%.+]], + #pragma omp simd reduction(*:R) +// CHECK: br label %[[SIMD_LOOP8_COND:[^,]+]] +// CHECK: [[SIMD_LOOP8_COND]] +// CHECK-NEXT: [[IV8:%.+]] = load i64, i64* [[OMP_IV8]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID:[0-9]+]] +// CHECK-NEXT: [[CMP8:%.+]] = icmp slt i64 [[IV8]], 7 +// CHECK-NEXT: br i1 [[CMP8]], label %[[SIMPLE_LOOP8_BODY:.+]], label %[[SIMPLE_LOOP8_END:[^,]+]] + for (long long i = -10; i < 10; i += 3) { +// CHECK: [[SIMPLE_LOOP8_BODY]] +// Start of body: calculate i from IV: +// CHECK: [[IV8_0:%.+]] = load i64, i64* [[OMP_IV8]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] +// CHECK-NEXT: [[LC_IT_1:%.+]] = mul nsw i64 [[IV8_0]], 3 +// CHECK-NEXT: [[LC_IT_2:%.+]] = add nsw i64 -10, [[LC_IT_1]] +// CHECK-NEXT: store i64 [[LC_IT_2]], i64* [[LC:%[^,]+]],{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] +// CHECK-NEXT: [[LC_VAL:%.+]] = load i64, i64* [[LC]]{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] +// CHECK: store i32 %{{.+}}, i32* [[R_PRIV]],{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] + R *= i; +// CHECK: [[IV8_2:%.+]] = load i64, i64* [[OMP_IV8]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] +// CHECK-NEXT: [[ADD8_2:%.+]] = add nsw i64 [[IV8_2]], 1 +// CHECK-NEXT: store i64 [[ADD8_2]], i64* [[OMP_IV8]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] + } +// CHECK: [[SIMPLE_LOOP8_END]] +// CHECK-NEXT: [[R_VAL:%.+]] = load i32, i32* [[R]], +// CHECK-NEXT: [[R_PRIV_VAL:%.+]] = load i32, i32* [[R_PRIV]], +// CHECK-NEXT: [[RED:%.+]] = mul nsw i32 [[R_VAL]], [[R_PRIV_VAL]] +// CHECK-NEXT: store i32 [[RED]], i32* [[R]], // CHECK-NEXT: ret void } |
