diff options
Diffstat (limited to 'clang/lib')
| -rw-r--r-- | clang/lib/CodeGen/CGBuiltin.cpp | 2 | ||||
| -rw-r--r-- | clang/lib/Headers/arm_neon.td | 12 |
2 files changed, 8 insertions, 6 deletions
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 703d353ac2f..c857e27d972 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -991,7 +991,6 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID, case ARM::BI__builtin_neon_vaddw_v: Int = usgn ? Intrinsic::arm_neon_vaddws : Intrinsic::arm_neon_vaddwu; return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vaddw"); - // FIXME: vbsl -> or ((0 & 1), (0 & 2)) in arm_neon.h case ARM::BI__builtin_neon_vcale_v: std::swap(Ops[0], Ops[1]); case ARM::BI__builtin_neon_vcage_v: { @@ -1218,7 +1217,6 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID, case ARM::BI__builtin_neon_vrecpsq_v: return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrecps, &Ty, 1), Ops, "vrecps"); - // FIXME: rev16, 32, 16 -> shufflevector case ARM::BI__builtin_neon_vrhadd_v: case ARM::BI__builtin_neon_vrhaddq_v: Int = usgn ? Intrinsic::arm_neon_vrhaddu : Intrinsic::arm_neon_vrhadds; diff --git a/clang/lib/Headers/arm_neon.td b/clang/lib/Headers/arm_neon.td index fb298a67c69..c833dc03100 100644 --- a/clang/lib/Headers/arm_neon.td +++ b/clang/lib/Headers/arm_neon.td @@ -40,6 +40,10 @@ def OP_HI : Op; def OP_LO : Op; def OP_CONC : Op; def OP_DUP : Op; +def OP_SEL : Op; +def OP_REV64 : Op; +def OP_REV32 : Op; +def OP_REV16 : Op; class Inst <string p, string t, Op o> { string Prototype = p; @@ -298,9 +302,9 @@ def VEXT : WInst<"dddi", "cUcPcsUsPsiUilUlQcQUcQPcQsQUsQPsQiQUiQlQUl">; //////////////////////////////////////////////////////////////////////////////// // E.3.27 Reverse vector elements (sdap endianness) -def VREV64 : WInst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf">; -def VREV32 : WInst<"dd", "csUcUsPcQcQsQUcQUsQPc">; -def VREV16 : WInst<"dd", "cUcPcQcQUcQPc">; +def VREV64 : Inst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", OP_REV64>; +def VREV32 : Inst<"dd", "csUcUsPcQcQsQUcQUsQPc", OP_REV32>; +def VREV16 : Inst<"dd", "cUcPcQcQUcQPc", OP_REV16>; //////////////////////////////////////////////////////////////////////////////// // E.3.28 Other single operand arithmetic @@ -322,7 +326,7 @@ def VORR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; def VEOR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; def VBIC : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; def VORN : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; -def VBSL : SInst<"dudd", "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; +def VBSL : Inst<"dudd", "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs", OP_SEL>; //////////////////////////////////////////////////////////////////////////////// // E.3.30 Transposition operations |
