diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 19 |
2 files changed, 0 insertions, 33 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 0b8994cdc69..9bbc3cc7000 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6499,14 +6499,6 @@ multiclass avx512_extend_common<bits<8> opc, string OpcodeStr, }//isCodeGenOnly } -// support full register inputs (like SSE paterns) -multiclass avx512_extend_lowering<SDPatternOperator OpNode, X86VectorVTInfo To, - X86VectorVTInfo From, SubRegIndex SubRegIdx> { - def : Pat<(To.VT (OpNode (From.VT From.RC:$src))), - (!cast<Instruction>(NAME#To.ZSuffix#"rr") - (EXTRACT_SUBREG From.RC:$src, SubRegIdx))>; -} - multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode, bit IsCodeGenOnly, string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> { @@ -6517,7 +6509,6 @@ multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info, v16i8x_info, i128mem, LdFrag, OpNode, IsCodeGenOnly>, - avx512_extend_lowering<OpNode, v16i16x_info, v32i8x_info, sub_xmm>, EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256; } let Predicates = [HasBWI] in { @@ -6537,7 +6528,6 @@ multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info, v16i8x_info, i64mem, LdFrag, OpNode, IsCodeGenOnly>, - avx512_extend_lowering<OpNode, v8i32x_info, v32i8x_info, sub_xmm>, EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { @@ -6557,7 +6547,6 @@ multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info, v16i8x_info, i32mem, LdFrag, OpNode, IsCodeGenOnly>, - avx512_extend_lowering<OpNode, v4i64x_info, v32i8x_info, sub_xmm>, EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { @@ -6577,7 +6566,6 @@ multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info, v8i16x_info, i128mem, LdFrag, OpNode, IsCodeGenOnly>, - avx512_extend_lowering<OpNode, v8i32x_info, v16i16x_info, sub_xmm>, EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { @@ -6597,7 +6585,6 @@ multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info, v8i16x_info, i64mem, LdFrag, OpNode, IsCodeGenOnly>, - avx512_extend_lowering<OpNode, v4i64x_info, v16i16x_info, sub_xmm>, EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { @@ -6618,7 +6605,6 @@ multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info, v4i32x_info, i128mem, LdFrag, OpNode, IsCodeGenOnly>, - avx512_extend_lowering<OpNode, v4i64x_info, v8i32x_info, sub_xmm>, EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256; } let Predicates = [HasAVX512] in { diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index bb2c33cd56e..586d9c3df38 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -5851,25 +5851,6 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtO def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))), (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>; } - // On AVX2, we also support 256bit inputs. - let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { - def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))), - (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>; - } - let Predicates = [HasAVX, NoVLX] in { - def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))), - (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>; - def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))), - (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>; - - def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))), - (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>; - def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))), - (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>; - - def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))), - (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>; - } // Simple Register-Memory patterns let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { |
