diff options
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 94004d3df04..11c9cddb28c 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1789,13 +1789,13 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { MipsTargetStreamer &TOut = getTargetStreamer(); - const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); + const unsigned Opcode = Inst.getOpcode(); + const MCInstrDesc &MCID = getInstDesc(Opcode); bool ExpandedJalSym = false; Inst.setLoc(IDLoc); if (MCID.isBranch() || MCID.isCall()) { - const unsigned Opcode = Inst.getOpcode(); MCOperand Offset; switch (Opcode) { @@ -1909,14 +1909,13 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, // SSNOP is deprecated on MIPS32r6/MIPS64r6 // We still accept it but it is a normal nop. - if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) { + if (hasMips32r6() && Opcode == Mips::SSNOP) { std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a " "nop instruction"); } if (hasCnMips()) { - const unsigned Opcode = Inst.getOpcode(); MCOperand Opnd; int Imm; @@ -1966,7 +1965,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, // not in the operands. unsigned FirstOp = 1; unsigned SecondOp = 2; - switch (Inst.getOpcode()) { + switch (Opcode) { default: break; case Mips::SDivIMacro: @@ -2012,8 +2011,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, } // For PIC code convert unconditional jump to unconditional branch. - if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) && - inPicMode()) { + if ((Opcode == Mips::J || Opcode == Mips::J_MM) && inPicMode()) { MCInst BInst; BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ); BInst.addOperand(MCOperand::createReg(Mips::ZERO)); @@ -2024,8 +2022,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, // This expansion is not in a function called by tryExpandInstruction() // because the pseudo-instruction doesn't have a distinct opcode. - if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) && - inPicMode()) { + if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) { warnIfNoMacro(IDLoc); const MCExpr *JalExpr = Inst.getOperand(0).getExpr(); @@ -2106,7 +2103,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, } // if load/store if (inMicroMipsMode()) { - if (MCID.mayLoad() && Inst.getOpcode() != Mips::LWP_MM) { + if (MCID.mayLoad() && Opcode != Mips::LWP_MM) { // Try to create 16-bit GP relative load instruction. for (unsigned i = 0; i < MCID.getNumOperands(); i++) { const MCOperandInfo &OpInfo = MCID.OpInfo[i]; @@ -2137,7 +2134,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, MCOperand Opnd; int Imm; - switch (Inst.getOpcode()) { + switch (Opcode) { default: break; case Mips::ADDIUSP_MM: @@ -2285,8 +2282,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, TOut.emitDirectiveSetReorder(); } - if ((Inst.getOpcode() == Mips::JalOneReg || - Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) && + if ((Opcode == Mips::JalOneReg || Opcode == Mips::JalTwoReg || + ExpandedJalSym) && isPicAndNotNxxAbi()) { if (IsCpRestoreSet) { // We need a NOP between the JALR and the LW: |
