diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/scavenging.mir | 2 |
2 files changed, 8 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 487a2d50bbe..67ed16758bb 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -341,9 +341,7 @@ def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", - "Does not support ARM mode execution", - [ModeThumb]>; - + "Does not support ARM mode execution">; //===----------------------------------------------------------------------===// // ARM ISAa. @@ -504,11 +502,13 @@ def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, FeatureNoARM, + ModeThumb, FeatureDB, FeatureMClass]>; def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, FeatureNoARM, + ModeThumb, FeatureDB, FeatureMClass]>; @@ -536,6 +536,7 @@ def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, FeatureThumb2, FeatureNoARM, + ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass]>; @@ -543,6 +544,7 @@ def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, FeatureThumb2, FeatureNoARM, + ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass, @@ -598,6 +600,7 @@ def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", [HasV8MBaselineOps, FeatureNoARM, + ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureV7Clrex, @@ -608,6 +611,7 @@ def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", [HasV8MMainlineOps, FeatureNoARM, + ModeThumb, FeatureDB, FeatureHWDivThumb, Feature8MSecExt, diff --git a/llvm/test/CodeGen/ARM/scavenging.mir b/llvm/test/CodeGen/ARM/scavenging.mir index 09040a3bd21..dfd02fbee75 100644 --- a/llvm/test/CodeGen/ARM/scavenging.mir +++ b/llvm/test/CodeGen/ARM/scavenging.mir @@ -1,4 +1,4 @@ -# RUN: llc -o - %s -mtriple=arm-arm-none-eabi -mcpu=cortex-m0 -run-pass scavenger-test | FileCheck %s +# RUN: llc -o - %s -mtriple=thumb-arm-none-eabi -mcpu=cortex-m0 -run-pass scavenger-test | FileCheck %s --- # CHECK-LABEL: name: scavengebug0 # Make sure we are not spilling/using a physreg used in the very last |
