diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/bitfield-extract.ll | 17 |
2 files changed, 18 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 9789193def8..9aa7c031e60 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -1681,7 +1681,7 @@ static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0, // later find more redundancy. Opd0 = N->getOperand(0).getOperand(0); TruncBits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits(); - VT = Opd0->getValueType(0); + VT = Opd0.getValueType(); assert(VT == MVT::i64 && "the promoted type should be i64"); } else if (BiggerPattern) { // Let's pretend a 0 shift left has been performed. diff --git a/llvm/test/CodeGen/AArch64/bitfield-extract.ll b/llvm/test/CodeGen/AArch64/bitfield-extract.ll index 5e727b669e2..69faf467d07 100644 --- a/llvm/test/CodeGen/AArch64/bitfield-extract.ll +++ b/llvm/test/CodeGen/AArch64/bitfield-extract.ll @@ -96,3 +96,20 @@ define void @test11(i64 %a) { } declare void @use(i16 signext, i64) + +; CHECK-LABEL: test_complex_node: +; CHECK: ldr d0, [x0], #8 +; CHECK: ubfx x[[VAL:[0-9]+]], x0, #5, #27 +; CHECK: str w[[VAL]], [x2] +define <2 x i32> @test_complex_node(<2 x i32>* %addr, <2 x i32>** %addr2, i32* %bf ) { + %vec = load <2 x i32>, <2 x i32>* %addr + + %vec.next = getelementptr <2 x i32>, <2 x i32>* %addr, i32 1 + store <2 x i32>* %vec.next, <2 x i32>** %addr2 + %lo = ptrtoint <2 x i32>* %vec.next to i32 + + %val = lshr i32 %lo, 5 + store i32 %val, i32* %bf + + ret <2 x i32> %vec +} |
