diff options
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsAArch64.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 28 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/hints.ll | 67 |
3 files changed, 89 insertions, 11 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index e3c0fb35990..050762b6114 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -33,6 +33,11 @@ def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; //===----------------------------------------------------------------------===// +// HINT + +def int_aarch64_hint : Intrinsic<[], [llvm_i32_ty]>; + +//===----------------------------------------------------------------------===// // RBIT def int_aarch64_rbit : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 5007172f153..0c9687eca56 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -776,15 +776,17 @@ def simdimmtype10 : Operand<i32>, // Base encoding for system instruction operands. let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in -class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands> - : I<oops, iops, asm, operands, "", []> { +class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands, + list<dag> pattern = []> + : I<oops, iops, asm, operands, "", pattern> { let Inst{31-22} = 0b1101010100; let Inst{21} = L; } // System instructions which do not have an Rt register. -class SimpleSystemI<bit L, dag iops, string asm, string operands> - : BaseSystemI<L, (outs), iops, asm, operands> { +class SimpleSystemI<bit L, dag iops, string asm, string operands, + list<dag> pattern = []> + : BaseSystemI<L, (outs), iops, asm, operands, pattern> { let Inst{4-0} = 0b11111; } @@ -797,13 +799,17 @@ class RtSystemI<bit L, dag oops, dag iops, string asm, string operands> } // Hint instructions that take both a CRm and a 3-bit immediate. -class HintI<string mnemonic> - : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "">, - Sched<[WriteHint]> { - bits <7> imm; - let Inst{20-12} = 0b000110010; - let Inst{11-5} = imm; -} +// NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot +// model patterns with sufficiently fine granularity +let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in + class HintI<string mnemonic> + : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "", + [(int_aarch64_hint imm0_127:$imm)]>, + Sched<[WriteHint]> { + bits <7> imm; + let Inst{20-12} = 0b000110010; + let Inst{11-5} = imm; + } // System instructions taking a single literal operand which encodes into // CRm. op2 differentiates the opcodes. diff --git a/llvm/test/CodeGen/AArch64/hints.ll b/llvm/test/CodeGen/AArch64/hints.ll new file mode 100644 index 00000000000..d7d9e23af1f --- /dev/null +++ b/llvm/test/CodeGen/AArch64/hints.ll @@ -0,0 +1,67 @@ +; RUN: llc -mtriple aarch64-eabi -o - %s | FileCheck %s + +declare void @llvm.aarch64.hint(i32) nounwind + +define void @hint_nop() { +entry: + tail call void @llvm.aarch64.hint(i32 0) nounwind + ret void +} + +; CHECK-LABEL: hint_nop +; CHECK: nop + +define void @hint_yield() { +entry: + tail call void @llvm.aarch64.hint(i32 1) nounwind + ret void +} + +; CHECK-LABEL: hint_yield +; CHECK: yield + +define void @hint_wfe() { +entry: + tail call void @llvm.aarch64.hint(i32 2) nounwind + ret void +} + +; CHECK-LABEL: hint_wfe +; CHECK: wfe + +define void @hint_wfi() { +entry: + tail call void @llvm.aarch64.hint(i32 3) nounwind + ret void +} + +; CHECK-LABEL: hint_wfi +; CHECK: wfi + +define void @hint_sev() { +entry: + tail call void @llvm.aarch64.hint(i32 4) nounwind + ret void +} + +; CHECK-LABEL: hint_sev +; CHECK: sev + +define void @hint_sevl() { +entry: + tail call void @llvm.aarch64.hint(i32 5) nounwind + ret void +} + +; CHECK-LABEL: hint_sevl +; CHECK: sevl + +define void @hint_undefined() { +entry: + tail call void @llvm.aarch64.hint(i32 8) nounwind + ret void +} + +; CHECK-LABEL: hint_undefined +; CHECK: hint #0x8 + |
