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-rw-r--r--llvm/include/llvm/IR/Intrinsics.td12
-rw-r--r--llvm/include/llvm/IR/IntrinsicsAArch64.td4
-rw-r--r--llvm/include/llvm/IR/IntrinsicsARM.td2
-rw-r--r--llvm/include/llvm/Target/TargetSelectionDAG.td6
-rw-r--r--llvm/test/TableGen/intrinsic-long-name.td2
-rw-r--r--llvm/test/TableGen/intrinsic-varargs.td2
-rw-r--r--llvm/utils/TableGen/CodeGenTarget.cpp2
7 files changed, 16 insertions, 14 deletions
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index d1d157be91b..94051b6f09f 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -240,7 +240,7 @@ class Intrinsic<list<LLVMType> ret_types,
string TargetPrefix = ""; // Set to a prefix for target-specific intrinsics.
list<LLVMType> RetTypes = ret_types;
list<LLVMType> ParamTypes = param_types;
- list<IntrinsicProperty> Properties = properties;
+ list<IntrinsicProperty> IntrProperties = properties;
bit isTarget = 0;
}
@@ -359,7 +359,7 @@ def int_memset : Intrinsic<[],
llvm_i32_ty, llvm_i1_ty],
[IntrReadWriteArgMem, NoCapture<0>]>;
-let Properties = [IntrNoMem] in {
+let IntrProperties = [IntrNoMem] in {
def int_fma : Intrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>]>;
@@ -421,7 +421,7 @@ def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
//
// None of these intrinsics accesses memory at all.
-let Properties = [IntrNoMem] in {
+let IntrProperties = [IntrNoMem] in {
def int_bswap: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
def int_ctpop: Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>]>;
def int_ctlz : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty]>;
@@ -435,7 +435,7 @@ let Properties = [IntrNoMem] in {
// None of these intrinsics accesses memory at all...but that doesn't mean the
// optimizers can change them aggressively. Special handling needed in a few
// places.
-let Properties = [IntrNoMem] in {
+let IntrProperties = [IntrNoMem] in {
def int_dbg_declare : Intrinsic<[],
[llvm_metadata_ty,
llvm_metadata_ty,
@@ -472,7 +472,7 @@ def int_eh_unwind_init: Intrinsic<[]>,
def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;
-let Properties = [IntrNoMem] in {
+let IntrProperties = [IntrNoMem] in {
def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>;
def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>;
}
@@ -597,7 +597,7 @@ def int_debugtrap : Intrinsic<[]>,
def int_donothing : Intrinsic<[], [], [IntrNoMem]>;
// Intrisics to support half precision floating point format
-let Properties = [IntrNoMem] in {
+let IntrProperties = [IntrNoMem] in {
def int_convert_to_fp16 : Intrinsic<[llvm_i16_ty], [llvm_anyfloat_ty]>;
def int_convert_from_fp16 : Intrinsic<[llvm_anyfloat_ty], [llvm_i16_ty]>;
}
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 578f259aae1..5489604565a 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -159,7 +159,7 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
// Arithmetic ops
-let Properties = [IntrNoMem] in {
+let IntrProperties = [IntrNoMem] in {
// Vector Add Across Lanes
def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
@@ -212,7 +212,7 @@ let Properties = [IntrNoMem] in {
// Vector Extending Multiply
def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
- let Properties = [IntrNoMem, Commutative];
+ let IntrProperties = [IntrNoMem, Commutative];
}
// Vector Saturating Doubling Long Multiply
diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td
index c1d911cefee..626d99be9c4 100644
--- a/llvm/include/llvm/IR/IntrinsicsARM.td
+++ b/llvm/include/llvm/IR/IntrinsicsARM.td
@@ -207,7 +207,7 @@ class Neon_Tbl6Arg_Intrinsic
// Arithmetic ops
-let Properties = [IntrNoMem, Commutative] in {
+let IntrProperties = [IntrNoMem, Commutative] in {
// Vector Add.
def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index fe998d61bdb..ac49b1fb724 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -300,7 +300,9 @@ def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
//===----------------------------------------------------------------------===//
// Selection DAG Pattern Operations
-class SDPatternOperator;
+class SDPatternOperator {
+ list<SDNodeProperty> Properties = [];
+}
//===----------------------------------------------------------------------===//
// Selection DAG Node definitions.
@@ -310,7 +312,7 @@ class SDNode<string opcode, SDTypeProfile typeprof,
: SDPatternOperator {
string Opcode = opcode;
string SDClass = sdclass;
- list<SDNodeProperty> Properties = props;
+ let Properties = props;
SDTypeProfile TypeProfile = typeprof;
}
diff --git a/llvm/test/TableGen/intrinsic-long-name.td b/llvm/test/TableGen/intrinsic-long-name.td
index 6b9ba018e38..38ebf13dbf3 100644
--- a/llvm/test/TableGen/intrinsic-long-name.td
+++ b/llvm/test/TableGen/intrinsic-long-name.td
@@ -19,7 +19,7 @@ class Intrinsic<string name, list<LLVMType> param_types = []> {
string TargetPrefix = "";
list<LLVMType> RetTypes = [];
list<LLVMType> ParamTypes = param_types;
- list<IntrinsicProperty> Properties = [];
+ list<IntrinsicProperty> IntrProperties = [];
}
def iAny : ValueType<0, 254>;
diff --git a/llvm/test/TableGen/intrinsic-varargs.td b/llvm/test/TableGen/intrinsic-varargs.td
index 42ce8a95962..0aafad8093c 100644
--- a/llvm/test/TableGen/intrinsic-varargs.td
+++ b/llvm/test/TableGen/intrinsic-varargs.td
@@ -19,7 +19,7 @@ class Intrinsic<string name, list<LLVMType> param_types = []> {
string TargetPrefix = "";
list<LLVMType> RetTypes = [];
list<LLVMType> ParamTypes = param_types;
- list<IntrinsicProperty> Properties = [];
+ list<IntrinsicProperty> IntrProperties = [];
}
// isVoid needs to match the definition in ValueTypes.td
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 8fc8f1fa3b5..167ed761781 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -565,7 +565,7 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
}
// Parse the intrinsic properties.
- ListInit *PropList = R->getValueAsListInit("Properties");
+ ListInit *PropList = R->getValueAsListInit("IntrProperties");
for (unsigned i = 0, e = PropList->size(); i != e; ++i) {
Record *Property = PropList->getElementAsRecord(i);
assert(Property->isSubClassOf("IntrinsicProperty") &&
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