diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/struct_byval.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/swift-atomics.ll | 4 |
3 files changed, 10 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 3111f5e385e..a8e62e5a559 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -133,8 +133,13 @@ void ARMSubtarget::resetSubtargetFeatures(const MachineFunction *MF) { } void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { - if (CPUString.empty()) - CPUString = "generic"; + if (CPUString.empty()) { + if (isTargetIOS() && !getTargetTriple().isOSVersionLT(6)) + // Default to Swift for iOS 6 or later versions. + CPUString = "swift"; + else + CPUString = "generic"; + } // Insert the architecture feature derived from the target triple into the // feature string. This is important for setting features that are implied diff --git a/llvm/test/CodeGen/ARM/struct_byval.ll b/llvm/test/CodeGen/ARM/struct_byval.ll index 012b9948537..0b3d7afe6cd 100644 --- a/llvm/test/CodeGen/ARM/struct_byval.ll +++ b/llvm/test/CodeGen/ARM/struct_byval.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-ios6.0 -mcpu=generic| FileCheck %s ; rdar://9877866 %struct.SmallStruct = type { i32, [8 x i32], [37 x i8] } diff --git a/llvm/test/CodeGen/ARM/swift-atomics.ll b/llvm/test/CodeGen/ARM/swift-atomics.ll index 1d718155710..883165fc024 100644 --- a/llvm/test/CodeGen/ARM/swift-atomics.ll +++ b/llvm/test/CodeGen/ARM/swift-atomics.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s -; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC +; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s +; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=generic < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC ; Release operations only need the store barrier provided by a "dmb ishst", |
