diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 29 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/neon-mul-accum-encoding.ll | 89 |
2 files changed, 104 insertions, 14 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index f90a11db94d..0426b1145dc 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -1337,10 +1337,11 @@ class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDNode MulOp, SDNode OpNode> : N3V<op24, op23, op21_20, op11_8, 0, op4, - (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, itin, - OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", - [(set DPR:$dst, (Ty (OpNode DPR:$src1, - (Ty (MulOp DPR:$src2, DPR:$src3)))))]>; + (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, + OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", + [(set DPR:$Vd, (Ty (OpNode DPR:$src1, + (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>; + class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDNode MulOp, SDNode ShOp> @@ -1358,24 +1359,24 @@ class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDNode MulOp, SDNode ShOp> : N3V<0, 1, op21_20, op11_8, 1, 0, - (outs DPR:$dst), - (ins DPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), + (outs DPR:$Vd), + (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane), NVMulSLFrm, itin, - OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst", - [(set (Ty DPR:$dst), + OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd", + [(set (Ty DPR:$Vd), (Ty (ShOp (Ty DPR:$src1), - (Ty (MulOp DPR:$src2, - (Ty (NEONvduplane (Ty DPR_8:$src3), + (Ty (MulOp DPR:$Vn, + (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))))]>; class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDNode MulOp, SDNode OpNode> : N3V<op24, op23, op21_20, op11_8, 1, op4, - (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, itin, - OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", - [(set QPR:$dst, (Ty (OpNode QPR:$src1, - (Ty (MulOp QPR:$src2, QPR:$src3)))))]>; + (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, + OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", + [(set QPR:$Vd, (Ty (OpNode QPR:$src1, + (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>; class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode MulOp, SDNode ShOp> diff --git a/llvm/test/MC/ARM/neon-mul-accum-encoding.ll b/llvm/test/MC/ARM/neon-mul-accum-encoding.ll new file mode 100644 index 00000000000..bcd4eb31d8e --- /dev/null +++ b/llvm/test/MC/ARM/neon-mul-accum-encoding.ll @@ -0,0 +1,89 @@ +; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s + +; CHECK: vmla_8xi8 +define <8 x i8> @vmla_8xi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C +; CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] + %tmp4 = mul <8 x i8> %tmp2, %tmp3 + %tmp5 = add <8 x i8> %tmp1, %tmp4 + ret <8 x i8> %tmp5 +} + +; CHECK: vmla_4xi16 +define <4 x i16> @vmla_4xi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C +; CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] + %tmp4 = mul <4 x i16> %tmp2, %tmp3 + %tmp5 = add <4 x i16> %tmp1, %tmp4 + ret <4 x i16> %tmp5 +} + +; CHECK: vmla_2xi32 +define <2 x i32> @vmla_2xi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C +; CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2] + %tmp4 = mul <2 x i32> %tmp2, %tmp3 + %tmp5 = add <2 x i32> %tmp1, %tmp4 + ret <2 x i32> %tmp5 +} + +; CHECK: vmla_2xfloat +define <2 x float> @vmla_2xfloat(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { + %tmp1 = load <2 x float>* %A + %tmp2 = load <2 x float>* %B + %tmp3 = load <2 x float>* %C +; CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] + %tmp4 = fmul <2 x float> %tmp2, %tmp3 + %tmp5 = fadd <2 x float> %tmp1, %tmp4 + ret <2 x float> %tmp5 +} + +; CHECK: vmla_16xi8 +define <16 x i8> @vmla_16xi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = load <16 x i8>* %C +; CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] + %tmp4 = mul <16 x i8> %tmp2, %tmp3 + %tmp5 = add <16 x i8> %tmp1, %tmp4 + ret <16 x i8> %tmp5 +} + +; CHECK: vmla_8xi16 +define <8 x i16> @vmla_8xi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = load <8 x i16>* %C +; CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] + %tmp4 = mul <8 x i16> %tmp2, %tmp3 + %tmp5 = add <8 x i16> %tmp1, %tmp4 + ret <8 x i16> %tmp5 +} + +; CHECK: vmla_4xi32 +define <4 x i32> @vmla_4xi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = load <4 x i32>* %C +; CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] + %tmp4 = mul <4 x i32> %tmp2, %tmp3 + %tmp5 = add <4 x i32> %tmp1, %tmp4 + ret <4 x i32> %tmp5 +} + +; CHECK: vmla_4xfloat +define <4 x float> @vmla_4xfloat(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { + %tmp1 = load <4 x float>* %A + %tmp2 = load <4 x float>* %B + %tmp3 = load <4 x float>* %C +; CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] + %tmp4 = fmul <4 x float> %tmp2, %tmp3 + %tmp5 = fadd <4 x float> %tmp1, %tmp4 + ret <4 x float> %tmp5 +} |
