diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-cvt.ll | 17 |
2 files changed, 24 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 557664c09dc..758ba3ab128 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1301,6 +1301,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal); setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal); setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); + setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom); + setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom); setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal); setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal); @@ -11793,6 +11795,11 @@ SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op, case MVT::v4i32: case MVT::v8i32: return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget); + case MVT::v16i8: + case MVT::v16i16: + if (Subtarget->hasAVX512()) + return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(), + DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0)); } llvm_unreachable(nullptr); } diff --git a/llvm/test/CodeGen/X86/avx512-cvt.ll b/llvm/test/CodeGen/X86/avx512-cvt.ll index 842b9f8494b..a211bcd38c9 100644 --- a/llvm/test/CodeGen/X86/avx512-cvt.ll +++ b/llvm/test/CodeGen/X86/avx512-cvt.ll @@ -308,3 +308,20 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) { %1 = sitofp <8 x i1> %cmpres to <8 x double> ret <8 x double> %1 } + +; CHECK-LABEL: @uitofp_16i8 +; CHECK: vpmovzxbd +; CHECK: vcvtudq2ps +define <16 x float> @uitofp_16i8(<16 x i8>%a) { + %b = uitofp <16 x i8> %a to <16 x float> + ret <16 x float>%b +} + +; CHECK-LABEL: @uitofp_16i16 +; CHECK: vpmovzxwd +; CHECK: vcvtudq2ps +define <16 x float> @uitofp_16i16(<16 x i16>%a) { + %b = uitofp <16 x i16> %a to <16 x float> + ret <16 x float>%b +} + |
