diff options
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index b5203a8c4fe..11710b42e60 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -367,7 +367,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, return true; } -unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const { +unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) { switch (MI.getOpcode()) { default: return AMDGPU::INSTRUCTION_LIST_END; case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE; diff --git a/llvm/lib/Target/R600/SIInstrInfo.h b/llvm/lib/Target/R600/SIInstrInfo.h index 84ebc963c30..4af63481e3a 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.h +++ b/llvm/lib/Target/R600/SIInstrInfo.h @@ -68,7 +68,7 @@ public: StringRef &ErrInfo) const; bool isSALUInstr(const MachineInstr &MI) const; - unsigned getVALUOp(const MachineInstr &MI) const; + static unsigned getVALUOp(const MachineInstr &MI); bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const; /// \brief Return the correct register class for \p OpNo. For target-specific |
