diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | 22 |
2 files changed, 25 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 0a795c99f94..32e83cb385f 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -604,7 +604,8 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { // We don't need to fix the PHI if the common dominator of the // two incoming blocks terminates with a uniform branch. - if (MI.getNumExplicitOperands() == 5) { + bool HasVGPROperand = phiHasVGPROperands(MI, MRI, TRI, TII); + if (MI.getNumExplicitOperands() == 5 && !HasVGPROperand) { MachineBasicBlock *MBB0 = MI.getOperand(2).getMBB(); MachineBasicBlock *MBB1 = MI.getOperand(4).getMBB(); @@ -649,8 +650,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { // is no chance for values to be over-written. SmallSet<unsigned, 8> Visited; - if (phiHasVGPROperands(MI, MRI, TRI, TII) || - !phiHasBreakDef(MI, MRI, Visited)) { + if (HasVGPROperand || !phiHasBreakDef(MI, MRI, Visited)) { DEBUG(dbgs() << "Fixing PHI: " << MI); TII->moveToVALU(MI); } diff --git a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll index 9416336a44e..3c25dc7f0e7 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -557,6 +557,28 @@ done: ret void } +; GCN-LABEL: {{^}}move_to_valu_vgpr_operand_phi: +; GCN: v_add_i32_e32 +; GCN: ds_write_b32 +define void @move_to_valu_vgpr_operand_phi(i32 addrspace(3)* %out) { +bb0: + br label %bb1 + +bb1: ; preds = %bb3, %bb0 + %tmp0 = phi i32 [ 8, %bb0 ], [ %tmp4, %bb3 ] + %tmp1 = add nsw i32 %tmp0, -1 + %tmp2 = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tmp1 + br i1 undef, label %bb2, label %bb3 + +bb2: ; preds = %bb1 + store volatile i32 1, i32 addrspace(3)* %tmp2, align 4 + br label %bb3 + +bb3: ; preds = %bb2, %bb1 + %tmp4 = add nsw i32 %tmp0, 2 + br label %bb1 +} + declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { nounwind readnone } |
