diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP2Instructions.td | 7 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/vop3-gfx9.s | 24 |
2 files changed, 30 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index ae8126aa886..44c4401d122 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -1340,13 +1340,18 @@ def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>; +} // End SubtargetPredicate = isGFX8GFX9 + +let SubtargetPredicate = isGFX9Only in { + defm : VOP2bInstAliases<V_ADD_I32_e32, V_ADD_CO_U32_e32_gfx9, "v_add_co_u32">; defm : VOP2bInstAliases<V_ADDC_U32_e32, V_ADDC_CO_U32_e32_gfx9, "v_addc_co_u32">; defm : VOP2bInstAliases<V_SUB_I32_e32, V_SUB_CO_U32_e32_gfx9, "v_sub_co_u32">; defm : VOP2bInstAliases<V_SUBB_U32_e32, V_SUBB_CO_U32_e32_gfx9, "v_subb_co_u32">; defm : VOP2bInstAliases<V_SUBREV_I32_e32, V_SUBREV_CO_U32_e32_gfx9, "v_subrev_co_u32">; defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">; -} // End SubtargetPredicate = isGFX8GFX9 + +} // End SubtargetPredicate = isGFX9Only let SubtargetPredicate = HasDLInsts in { diff --git a/llvm/test/MC/AMDGPU/vop3-gfx9.s b/llvm/test/MC/AMDGPU/vop3-gfx9.s index 2fca0de076e..bec430e8819 100644 --- a/llvm/test/MC/AMDGPU/vop3-gfx9.s +++ b/llvm/test/MC/AMDGPU/vop3-gfx9.s @@ -491,6 +491,30 @@ v_subrev_co_u32 v84, vcc, v13, v31 clamp // GFX9: v_subrev_co_u32_e64 v84, vcc, v13, v31 clamp ; encoding: [0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00] // NOVI: error: +v_addc_co_u32 v84, vcc, v13, v31, vcc +// GFX9: v_addc_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x38] +// NOVI: error: instruction not supported on this GPU + +v_subb_co_u32 v84, vcc, v13, v31, vcc +// GFX9: v_subb_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3a] +// NOVI: error: instruction not supported on this GPU + +v_subbrev_co_u32 v84, vcc, v13, v31, vcc +// GFX9: v_subbrev_co_u32_e32 v84, vcc, v13, v31, vcc ; encoding: [0x0d,0x3f,0xa8,0x3c] +// NOVI: error: instruction not supported on this GPU + +v_add_co_u32 v84, vcc, v13, v31 +// GFX9: v_add_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x32] +// NOVI: error: instruction not supported on this GPU + +v_sub_co_u32 v84, vcc, v13, v31 +// GFX9: v_sub_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x34] +// NOVI: error: instruction not supported on this GPU + +v_subrev_co_u32 v84, vcc, v13, v31 +// GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36] +// NOVI: error: instruction not supported on this GPU + //===----------------------------------------------------------------------===// // Validate register size checks (bug 37943) //===----------------------------------------------------------------------===// |
