diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/basic-thumb2-instructions.s | 16 |
3 files changed, 30 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 45471a4e95b..53db5acbe80 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -4756,6 +4756,16 @@ def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift", def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift", (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; +// Aliases for the above with the .w qualifier +def : t2InstAlias<"mov${p}.w $Rd, $shift", + (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; +def : t2InstAlias<"movs${p}.w $Rd, $shift", + (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; +def : t2InstAlias<"mov${p}.w $Rd, $shift", + (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; +def : t2InstAlias<"movs${p}.w $Rd, $shift", + (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; + // ADR w/o the .w suffix def : t2InstAlias<"adr${p} $Rd, $addr", (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 51e0118469b..891b5c60e1f 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -8160,7 +8160,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst, isARMLowRegister(Inst.getOperand(1).getReg()) && isARMLowRegister(Inst.getOperand(2).getReg()) && Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && - inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) + inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) && + !HasWideQualifier) isNarrow = true; MCInst TmpInst; unsigned newOpc; @@ -8194,7 +8195,8 @@ bool ARMAsmParser::processInstruction(MCInst &Inst, bool isNarrow = false; if (isARMLowRegister(Inst.getOperand(0).getReg()) && isARMLowRegister(Inst.getOperand(1).getReg()) && - inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) + inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) && + !HasWideQualifier) isNarrow = true; MCInst TmpInst; unsigned newOpc; diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s index af1b6289755..b1cb53cdace 100644 --- a/llvm/test/MC/ARM/basic-thumb2-instructions.s +++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s @@ -1497,13 +1497,21 @@ _func: @ MOV(shifted register) @------------------------------------------------------------------------------ mov r6, r2, lsl #16 + mov.w r6, r2, lsl #16 mov r6, r2, lsr #16 + mov.w r6, r2, lsr #16 movs r6, r2, asr #32 + movs.w r6, r2, asr #32 movs r6, r2, ror #5 + movs.w r6, r2, ror #5 movs r4, r4, lsl r5 + movs.w r4, r4, lsl r5 movs r4, r4, lsr r5 + movs.w r4, r4, lsr r5 movs r4, r4, asr r5 + movs.w r4, r4, asr r5 movs r4, r4, ror r5 + movs.w r4, r4, ror r5 mov r4, r4, lsl r5 movs r4, r4, ror r8 movs r4, r5, lsr r6 @@ -1515,13 +1523,21 @@ _func: mov r4, r4, rrx @ CHECK: lsl.w r6, r2, #16 @ encoding: [0x4f,0xea,0x02,0x46] +@ CHECK: lsl.w r6, r2, #16 @ encoding: [0x4f,0xea,0x02,0x46] +@ CHECK: lsr.w r6, r2, #16 @ encoding: [0x4f,0xea,0x12,0x46] @ CHECK: lsr.w r6, r2, #16 @ encoding: [0x4f,0xea,0x12,0x46] @ CHECK: asrs r6, r2, #32 @ encoding: [0x16,0x10] +@ CHECK: asrs.w r6, r2, #32 @ encoding: [0x5f,0xea,0x22,0x06] +@ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16] @ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16] @ CHECK: lsls r4, r5 @ encoding: [0xac,0x40] +@ CHECK: lsls.w r4, r4, r5 @ encoding: [0x14,0xfa,0x05,0xf4] @ CHECK: lsrs r4, r5 @ encoding: [0xec,0x40] +@ CHECK: lsrs.w r4, r4, r5 @ encoding: [0x34,0xfa,0x05,0xf4] @ CHECK: asrs r4, r5 @ encoding: [0x2c,0x41] +@ CHECK: asrs.w r4, r4, r5 @ encoding: [0x54,0xfa,0x05,0xf4] @ CHECK: rors r4, r5 @ encoding: [0xec,0x41] +@ CHECK: rors.w r4, r4, r5 @ encoding: [0x74,0xfa,0x05,0xf4] @ CHECK: lsl.w r4, r4, r5 @ encoding: [0x04,0xfa,0x05,0xf4] @ CHECK: rors.w r4, r4, r8 @ encoding: [0x74,0xfa,0x08,0xf4] @ CHECK: lsrs.w r4, r5, r6 @ encoding: [0x35,0xfa,0x06,0xf4] |
