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-rw-r--r--llvm/lib/Target/X86/X86InstrCompiler.td4
-rw-r--r--llvm/test/CodeGen/X86/i16lshr8pat.ll32
2 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index 66326eaf50b..42235a497ce 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -1550,6 +1550,10 @@ def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
sub_8bit_hi)>,
Requires<[Not64BitMode]>;
+def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))),
+ (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
+ sub_8bit_hi)>,
+ Requires<[Not64BitMode]>;
def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
sub_8bit_hi)>,
diff --git a/llvm/test/CodeGen/X86/i16lshr8pat.ll b/llvm/test/CodeGen/X86/i16lshr8pat.ll
new file mode 100644
index 00000000000..7f2da8e2953
--- /dev/null
+++ b/llvm/test/CodeGen/X86/i16lshr8pat.ll
@@ -0,0 +1,32 @@
+; RUN: llc -march=x86 -stop-after expand-isel-pseudos <%s 2>&1 | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+; This test checks to make sure the lshr in %then1 block gets expanded using
+; GR16_ABCD pattern rather than GR32_ABCD pattern. By using the 16-bit pattern
+; this doesn't make the register liveness information look like the whole
+; 32-bit register is a live value, and allows generally better live register
+; analysis.
+; CHECK-LABEL: bb.1.then1:
+; CHECK-NOT: IMPLICIT_DEF
+; CHECK-NOT: INSERT_SUBREG
+; CHECK: sub_8bit_hi
+; CHECK-LABEL: bb.2.endif1:
+
+define i16 @foo4(i32 %prec, i8 *%dst, i16 *%src) {
+entry:
+ %cnd = icmp ne i32 %prec, 0
+ %t0 = load i16, i16 *%src, align 2
+ br i1 %cnd, label %then1, label %endif1
+
+then1:
+ %shr = lshr i16 %t0, 8
+ %conv = trunc i16 %shr to i8
+ store i8 %conv, i8 *%dst, align 1
+ br label %endif1
+
+endif1:
+ %t2 = phi i16 [0, %then1], [%t0, %entry]
+ ret i16 %t2
+}
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