diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sjlj-eh.ll | 7 |
2 files changed, 5 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5c9534c6fd2..31c2b63c099 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -26576,17 +26576,13 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI, BuildMI(DispatchBB, DL, TII->get(X86::CMP32ri)) .addReg(IReg) .addImm(LPadList.size()); - BuildMI(DispatchBB, DL, TII->get(X86::JA_1)).addMBB(TrapBB); + BuildMI(DispatchBB, DL, TII->get(X86::JAE_1)).addMBB(TrapBB); - unsigned JReg = MRI->createVirtualRegister(&X86::GR32RegClass); - BuildMI(DispContBB, DL, TII->get(X86::SUB32ri), JReg) - .addReg(IReg) - .addImm(1); BuildMI(DispContBB, DL, TII->get(Subtarget.is64Bit() ? X86::JMP64m : X86::JMP32m)) .addReg(0) .addImm(Subtarget.is64Bit() ? 8 : 4) - .addReg(JReg) + .addReg(IReg) .addJumpTableIndex(MJTI) .addReg(0); diff --git a/llvm/test/CodeGen/X86/sjlj-eh.ll b/llvm/test/CodeGen/X86/sjlj-eh.ll index 79bd450dcfb..35a11da7f4c 100644 --- a/llvm/test/CodeGen/X86/sjlj-eh.ll +++ b/llvm/test/CodeGen/X86/sjlj-eh.ll @@ -60,13 +60,12 @@ try.cont: ; ; CHECK: [[RESUME]]: ; CHECK: leal -64(%ebp), %esi -; assert(UFC.__callsite <= 1); +; assert(UFC.__callsite < 1); ; CHECK: movl -60(%ebp), %eax ; CHECK: cmpl $1, %eax -; CHECK: jbe [[CONT:LBB[0-9]+_[0-9]+]] +; CHECK: jb [[CONT:LBB[0-9]+_[0-9]+]] ; CHECK: ud2 ; CHECK: [[CONT]]: -; *Handlers[--UFC.__callsite] -; CHECK: subl $1, %eax +; *Handlers[UFC.__callsite] ; CHECK: jmpl *LJTI |
