diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 18 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/fcmp.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/sub.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/tailcall/tailcall.ll | 2 |
4 files changed, 13 insertions, 16 deletions
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index 07dfff53bf3..e06b57e4183 100644 --- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -597,21 +597,14 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool InMicroMipsMode = STI.inMicroMipsMode(); const MipsInstrInfo *TII = STI.getInstrInfo(); - if (InMicroMipsMode && STI.hasMips32r6()) { - // This is microMIPS32r6 or microMIPS64r6 processor. Delay slot for - // branching instructions is not needed. - return Changed; - } - for (Iter I = MBB.begin(); I != MBB.end(); ++I) { if (!hasUnoccupiedSlot(&*I)) continue; - ++FilledSlots; - Changed = true; + // Delay slot filling is disabled at -O0, or in microMIPS32R6. + if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) && + !(InMicroMipsMode && STI.hasMips32r6())) { - // Delay slot filling is disabled at -O0. - if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None)) { bool Filled = false; if (MipsCompactBranchPolicy.getValue() != CB_Always || @@ -643,6 +636,8 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { // if it is in range. DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode()))); } + ++FilledSlots; + Changed = true; continue; } } @@ -660,12 +655,15 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { (STI.hasMips32r6() && MipsCompactBranchPolicy != CB_Never)) && TII->getEquivalentCompactForm(I)) { I = replaceWithCompactBranch(MBB, I, I->getDebugLoc()); + Changed = true; continue; } // Bundle the NOP to the instruction with the delay slot. BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); MIBundleBuilder(MBB, I, std::next(I, 2)); + ++FilledSlots; + Changed = true; } return Changed; diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll index eb6c06db4ef..e5c40f2bfd4 100644 --- a/llvm/test/CodeGen/Mips/fcmp.ll +++ b/llvm/test/CodeGen/Mips/fcmp.ll @@ -1100,7 +1100,7 @@ entry: ; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]] ; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]] ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 -; MM32R6-DAG: bnez $[[T5]], +; MM32R6-DAG: bnezc $[[T5]], ; MM64R6-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI32_0) @@ -1112,7 +1112,7 @@ entry: ; MM64R6-DAG: cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]] ; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]] ; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1 -; MM64R6-DAG: bnez $[[T9]], +; MM64R6-DAG: bnezc $[[T9]], %add = fadd fast float %at, %angle %cmp = fcmp ogt float %add, 1.000000e+00 @@ -1170,7 +1170,7 @@ entry: ; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]] ; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]] ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 -; MM32R6-DAG: bnez $[[T5]], +; MM32R6-DAG: bnezc $[[T5]], ; MM64R6-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI33_0) @@ -1182,7 +1182,7 @@ entry: ; MM64R6-DAG: cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]] ; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]] ; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1 -; MM64R6-DAG: bnez $[[T9]], +; MM64R6-DAG: bnezc $[[T9]], %add = fadd fast double %at, %angle %cmp = fcmp ogt double %add, 1.000000e+00 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll index 655addb10a6..2ab7225f445 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll @@ -222,7 +222,6 @@ entry: ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 ; MM64: dsubu $2, $[[T0]], $[[T3]] ; MM64: dsubu $3, $5, $7 -; MM64: jr $ra %r = sub i128 %a, %b ret i128 %r diff --git a/llvm/test/CodeGen/Mips/tailcall/tailcall.ll b/llvm/test/CodeGen/Mips/tailcall/tailcall.ll index 1c81335937d..eafbd10f5e3 100644 --- a/llvm/test/CodeGen/Mips/tailcall/tailcall.ll +++ b/llvm/test/CodeGen/Mips/tailcall/tailcall.ll @@ -169,7 +169,7 @@ entry: ; STATIC32MMR6: bc ; PIC64: jr $25 ; PIC64R6: jrc $25 -; PIC64R6MM: jr $25 +; PIC64R6MM: jrc $25 ; STATIC64: j ; PIC16: jalrc |
