diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 2 |
3 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td index 21c62af9a6a..0d444dfc9fa 100644 --- a/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td +++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -10,7 +10,7 @@ class MMDSPInst<string opstr = ""> : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { let ASEPredicate = [HasDSP]; - let AdditionalPredicates = [InMicroMips]; + let EncodingPredicates = [InMicroMips]; string BaseOpcode = opstr; string Arch = "mmdsp"; let DecoderNamespace = "MicroMips"; diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td index 04f1e66bfd8..132de6be750 100644 --- a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -417,11 +417,11 @@ class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm, NoItinerary>; let DecoderNamespace = "MicroMipsDSP", Arch = "mmdsp", - AdditionalPredicates = [HasDSP, InMicroMips] in { - def LWDSP_MM : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, - LW_FM_MM<0x3f>; - def SWDSP_MM : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, - LW_FM_MM<0x3e>; + EncodingPredicates = [InMicroMips], ASEPredicate = [HasDSP] in { + def LWDSP_MM : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, + LW_FM_MM<0x3f>; + def SWDSP_MM : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, + LW_FM_MM<0x3e>; } // Instruction defs. // microMIPS DSP Rev 1 @@ -531,7 +531,7 @@ def MODSUB_MM : DspMMRel, MODSUB_MM_ENC, MODSUB_DESC; def MULSAQ_S_W_PH_MM : DspMMRel, MULSAQ_S_W_PH_MM_ENC, MULSAQ_S_W_PH_DESC; def BITREV_MM : DspMMRel, BITREV_MM_ENC, BITREV_MM_DESC; def BPOSGE32_MM : DspMMRel, BPOSGE32_MM_ENC, BPOSGE32_MM_DESC, - ISA_MIPS1_NOT_32R6_64R6; + ISA_MICROMIPS32_NOT_MIPS32R6; def CMP_EQ_PH_MM : DspMMRel, CMP_EQ_PH_MM_ENC, CMP_EQ_PH_DESC; def CMP_LT_PH_MM : DspMMRel, CMP_LT_PH_MM_ENC, CMP_LT_PH_DESC; def CMP_LE_PH_MM : DspMMRel, CMP_LE_PH_MM_ENC, CMP_LE_PH_DESC; diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td index 51603206902..b9824220b55 100644 --- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td @@ -1289,7 +1289,7 @@ let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { } let DecoderNamespace = "MipsDSP", Arch = "dsp", - AdditionalPredicates = [HasDSP] in { + ASEPredicate = [HasDSP] in { def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>; def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>; } |
