diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/barrier-elimination.ll | 30 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/indirect-private-64.ll | 2 |
3 files changed, 42 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 36f16e3ca9a..3052439358a 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3159,6 +3159,17 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, SDValue Cast = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Src); return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, Cast); } + case Intrinsic::amdgcn_s_barrier: { + if (getTargetMachine().getOptLevel() > CodeGenOpt::None) { + const MachineFunction &MF = DAG.getMachineFunction(); + const SISubtarget &ST = MF.getSubtarget<SISubtarget>(); + unsigned WGSize = ST.getFlatWorkGroupSizes(*MF.getFunction()).second; + if (WGSize <= ST.getWavefrontSize()) + return SDValue(DAG.getMachineNode(AMDGPU::WAVE_BARRIER, DL, MVT::Other, + Op.getOperand(0)), 0); + } + return SDValue(); + }; default: return Op; } diff --git a/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll b/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll new file mode 100644 index 00000000000..c526baaab9c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/barrier-elimination.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=amdgcn < %s | FileCheck %s + +; CHECK-LABEL: {{^}}unknown_wgs: +; CHECK: s_barrier +define amdgpu_kernel void @unknown_wgs() { + tail call void @llvm.amdgcn.s.barrier() #0 + ret void +} + +; CHECK-LABEL: {{^}}flat_wgs_attr_32_128: +; CHECK: s_barrier +define amdgpu_kernel void @flat_wgs_attr_32_128() #1 { + tail call void @llvm.amdgcn.s.barrier() #0 + ret void +} + +; CHECK-LABEL: {{^}}flat_wgs_attr_32_64: +; CHECK: : +; CHECK-NEXT: ; wave barrier +; CHECK-NEXT: s_endpgm +define amdgpu_kernel void @flat_wgs_attr_32_64() #2 { + tail call void @llvm.amdgcn.s.barrier() #0 + ret void +} + +declare void @llvm.amdgcn.s.barrier() #0 + +attributes #0 = { convergent nounwind } +attributes #1 = { nounwind "amdgpu-flat-work-group-size"="32,128" } +attributes #2 = { nounwind "amdgpu-flat-work-group-size"="32,64" } diff --git a/llvm/test/CodeGen/AMDGPU/indirect-private-64.ll b/llvm/test/CodeGen/AMDGPU/indirect-private-64.ll index b6dea01cab4..7f08a89d149 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-private-64.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-private-64.ll @@ -121,4 +121,4 @@ define amdgpu_kernel void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* n } attributes #0 = { convergent nounwind } -attributes #1 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="64,64" } +attributes #1 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="64,128" } |
