diff options
| -rw-r--r-- | llvm/include/llvm/Target/MRegisterInfo.h | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/PrologEpilogInserter.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterInfo.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterInfo.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterInfo.td | 16 |
5 files changed, 15 insertions, 13 deletions
diff --git a/llvm/include/llvm/Target/MRegisterInfo.h b/llvm/include/llvm/Target/MRegisterInfo.h index 7d412292b38..8dbb13628ca 100644 --- a/llvm/include/llvm/Target/MRegisterInfo.h +++ b/llvm/include/llvm/Target/MRegisterInfo.h @@ -394,7 +394,7 @@ public: /// requiresRegisterScavenging - returns true if the target requires (and /// can make use of) the register scavenger. - virtual bool requiresRegisterScavenging() const { + virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { return false; } diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 9a25859a500..7cab34c950c 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -442,7 +442,7 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) { const TargetMachine &TM = Fn.getTarget(); assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!"); const MRegisterInfo &MRI = *TM.getRegisterInfo(); - RegScavenger *RS = MRI.requiresRegisterScavenging() ? new RegScavenger():NULL; + RegScavenger *RS=MRI.requiresRegisterScavenging(Fn) ? new RegScavenger():NULL; for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { if (RS) RS->reset(BB); diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp index c888034b410..2c53bfd6938 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp @@ -326,8 +326,10 @@ BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const { return Reserved; } -bool ARMRegisterInfo::requiresRegisterScavenging() const { - return EnableScavenging; +bool +ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { + const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); + return EnableScavenging && !AFI->isThumbFunction(); } /// hasFP - Return true if the specified function should have a dedicated frame diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.h b/llvm/lib/Target/ARM/ARMRegisterInfo.h index 23805a30155..0193093025f 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.h +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.h @@ -74,7 +74,7 @@ public: BitVector getReservedRegs(const MachineFunction &MF) const; - bool requiresRegisterScavenging() const; + bool requiresRegisterScavenging(const MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const; diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td index 625e3d3afb5..2e859eca3a6 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.td +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td @@ -163,14 +163,14 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, return THUMB_GPR_AO; if (Subtarget.useThumbBacktraces()) { if (Subtarget.isR9Reserved()) - return RI->requiresRegisterScavenging() ? ARM_GPR_AO_8 : ARM_GPR_AO_4; + return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_8:ARM_GPR_AO_4; else - return RI->requiresRegisterScavenging() ? ARM_GPR_AO_7 : ARM_GPR_AO_3; + return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_7:ARM_GPR_AO_3; } else { if (Subtarget.isR9Reserved()) - return RI->requiresRegisterScavenging() ? ARM_GPR_AO_6 : ARM_GPR_AO_2; + return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_6:ARM_GPR_AO_2; else - return RI->requiresRegisterScavenging() ? ARM_GPR_AO_5 : ARM_GPR_AO_1; + return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_5:ARM_GPR_AO_1; } } @@ -184,24 +184,24 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned)); else if (Subtarget.useThumbBacktraces()) { if (Subtarget.isR9Reserved()) { - if (RI->requiresRegisterScavenging()) + if (RI->requiresRegisterScavenging(MF)) I = ARM_GPR_AO_8 + (sizeof(ARM_GPR_AO_8)/sizeof(unsigned)); else I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned)); } else { - if (RI->requiresRegisterScavenging()) + if (RI->requiresRegisterScavenging(MF)) I = ARM_GPR_AO_7 + (sizeof(ARM_GPR_AO_7)/sizeof(unsigned)); else I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned)); } } else { if (Subtarget.isR9Reserved()) { - if (RI->requiresRegisterScavenging()) + if (RI->requiresRegisterScavenging(MF)) I = ARM_GPR_AO_6 + (sizeof(ARM_GPR_AO_6)/sizeof(unsigned)); else I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned)); } else { - if (RI->requiresRegisterScavenging()) + if (RI->requiresRegisterScavenging(MF)) I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned)); else I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned)); |
