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-rw-r--r--llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp11
-rw-r--r--llvm/lib/Target/ARM/ARMLegalizerInfo.cpp7
-rw-r--r--llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir121
3 files changed, 137 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index c7118201b75..200d6b8abec 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -103,6 +103,9 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
case TargetOpcode::G_FPOW:
return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
+ case TargetOpcode::G_FMA:
+ assert((Size == 32 || Size == 64) && "Unsupported size");
+ return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
}
llvm_unreachable("Unknown libcall function");
}
@@ -127,9 +130,12 @@ static LegalizerHelper::LegalizeResult
simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
Type *OpType) {
auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
+
+ SmallVector<CallLowering::ArgInfo, 3> Args;
+ for (unsigned i = 1; i < MI.getNumOperands(); i++)
+ Args.push_back({MI.getOperand(i).getReg(), OpType});
return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
- {{MI.getOperand(1).getReg(), OpType},
- {MI.getOperand(2).getReg(), OpType}});
+ Args);
}
LegalizerHelper::LegalizeResult
@@ -157,6 +163,7 @@ LegalizerHelper::libcall(MachineInstr &MI) {
case TargetOpcode::G_FSUB:
case TargetOpcode::G_FMUL:
case TargetOpcode::G_FDIV:
+ case TargetOpcode::G_FMA:
case TargetOpcode::G_FPOW:
case TargetOpcode::G_FREM: {
Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index fa5a8575710..3e694b80f80 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -198,6 +198,13 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
setFCmpLibcallsGNU();
}
+ if (!ST.useSoftFloat() && ST.hasVFP4())
+ for (auto Ty : {s32, s64})
+ setAction({G_FMA, Ty}, Legal);
+ else
+ for (auto Ty : {s32, s64})
+ setAction({G_FMA, Ty}, Libcall);
+
for (unsigned Op : {G_FREM, G_FPOW})
for (auto Ty : {s32, s64})
setAction({Op, Ty}, Libcall);
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
new file mode 100644
index 00000000000..5fe0d86b2b4
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
@@ -0,0 +1,121 @@
+# RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp4 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD
+# RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix HARD-ABI
+# RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp4,+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-ABI
+# RUN: llc -mtriple arm-linux-gnu -mattr=+vfp4,+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-ABI
+--- |
+ define void @test_fma_float() { ret void }
+ define void @test_fma_double() { ret void }
+...
+---
+name: test_fma_float
+# CHECK-LABEL: name: test_fma_float
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1, %r2
+
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[Z:%[0-9]+]]:_(s32) = COPY %r2
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = COPY %r2
+ ; HARD: [[R:%[0-9]+]]:_(s32) = G_FMA [[X]], [[Y]], [[Z]]
+ ; SOFT-NOT: G_FMA
+ ; SOFT: ADJCALLSTACKDOWN
+ ; SOFT-ABI-DAG: %r0 = COPY [[X]]
+ ; SOFT-ABI-DAG: %r1 = COPY [[Y]]
+ ; SOFT-ABI-DAG: %r2 = COPY [[Z]]
+ ; SOFT-ABI: BL &fmaf, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit-def %r0
+ ; SOFT-ABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; HARD-ABI-DAG: %s0 = COPY [[X]]
+ ; HARD-ABI-DAG: %s1 = COPY [[Y]]
+ ; HARD-ABI-DAG: %s2 = COPY [[Z]]
+ ; HARD-ABI: BL &fmaf, {{.*}}, implicit %s0, implicit %s1, implicit %s2, implicit-def %s0
+ ; HARD-ABI: [[R:%[0-9]+]]:_(s32) = COPY %s0
+ ; SOFT: ADJCALLSTACKUP
+ ; SOFT-NOT: G_FMA
+ %3(s32) = G_FMA %0, %1, %2
+ ; CHECK: %r0 = COPY [[R]]
+ %r0 = COPY %3(s32)
+ BX_RET 14, %noreg, implicit %r0
+...
+---
+name: test_fma_double
+# CHECK-LABEL: name: test_fma_double
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
+ - { id: 6, class: _ }
+ - { id: 7, class: _ }
+ - { id: 8, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1, %r2, %r3
+
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = COPY %r2
+ %3(s32) = COPY %r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
+ ; HARD-ABI-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
+ ; HARD-ABI-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
+ %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+ ; HARD: [[R:%[0-9]+]]:_(s64) = G_FMA [[X]], [[X]], [[Y]]
+ ; SOFT-NOT: G_FMA
+ ; SOFT: ADJCALLSTACKDOWN
+ ; SOFT-ABI-DAG: %r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-ABI-DAG: %r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-ABI-DAG: %r{{[2-3]}} = COPY [[X0]]
+ ; SOFT-ABI-DAG: %r{{[2-3]}} = COPY [[X1]]
+ ; SOFT-ABI: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+ ; SOFT-ABI: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SOFT-ABI: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
+ ; SOFT-ABI: G_STORE [[Y0]](s32), [[FI1]](p0){{.*}}store 8 into stack
+ ; SOFT-ABI: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; SOFT-ABI: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[FI1]], [[OFF2]](s32)
+ ; SOFT-ABI: G_STORE [[Y1]](s32), [[FI2]](p0){{.*}}store 8 into stack
+ ; SOFT-ABI: BL &fma, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-ABI-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-ABI-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; HARD-ABI-DAG: %d0 = COPY [[X]]
+ ; HARD-ABI-DAG: %d1 = COPY [[X]]
+ ; HARD-ABI-DAG: %d2 = COPY [[Y]]
+ ; HARD-ABI: BL &fma, {{.*}}, implicit %d0, implicit %d1, implicit %d2, implicit-def %d0
+ ; HARD-ABI: [[R:%[0-9]+]]:_(s64) = COPY %d0
+ ; SOFT: ADJCALLSTACKUP
+ ; SOFT-NOT: G_FMA
+ %6(s64) = G_FMA %4, %4, %5
+ ; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
+ ; HARD-ABI: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
+ %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
+ ; CHECK-DAG: %r0 = COPY [[R0]]
+ ; CHECK-DAG: %r1 = COPY [[R1]]
+ %r0 = COPY %7(s32)
+ %r1 = COPY %8(s32)
+ BX_RET 14, %noreg, implicit %r0, implicit %r1
+...
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