diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb/long.ll | 12 |
2 files changed, 4 insertions, 16 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index a13ef5820bf..15ae0c7940b 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -9788,8 +9788,8 @@ static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG, if (Subtarget->isThumb1Only()) { SDValue RHS = N->getOperand(1); if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { - int32_t imm = C->getSExtValue(); - if (-imm > 0) { + int64_t imm = C->getSExtValue(); + if (imm < 0) { SDLoc DL(N); RHS = DAG.getConstant(-imm, DL, MVT::i32); unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC @@ -9806,8 +9806,8 @@ static SDValue PerformAddeSubeCombine(SDNode *N, SelectionDAG &DAG, if (Subtarget->isThumb1Only()) { SDValue RHS = N->getOperand(1); if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { - int32_t imm = C->getSExtValue(); - if (-imm > 0) { + int64_t imm = C->getSExtValue(); + if (imm < 0) { SDLoc DL(N); // The with-carry-in form matches bitwise not instead of the negation. diff --git a/llvm/test/CodeGen/Thumb/long.ll b/llvm/test/CodeGen/Thumb/long.ll index c549bd425aa..e35f7cc82b1 100644 --- a/llvm/test/CodeGen/Thumb/long.ll +++ b/llvm/test/CodeGen/Thumb/long.ll @@ -194,15 +194,3 @@ entry: ; CHECK: movs r1, r3 } -; "sub 2147483648" has to be lowered into "add -2147483648" -define i64 @f12(i64 %x, i64 %y) { -entry: - %tmp1 = sub i64 %x, 2147483648 - ret i64 %tmp1 -; CHECK-LABEL: f12: -; CHECK: movs r2, #1 -; CHECK: lsls r2, r2, #31 -; CHECK: movs r3, #0 -; CHECK: adds r0, r0, r2 -; CHECK: sbcs r1, r3 -} |
