diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/known-bits.ll | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index b9f6fc0f1ab..9e802b99ed4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2506,6 +2506,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, LLVM_FALLTHROUGH; } case ISD::ADD: + case ISD::ADDC: case ISD::ADDE: { // Output known-0 bits are known if clear or set in both the low clear bits // common to both LHS & RHS. For example, 8+(X<<3) is known to have the @@ -2526,7 +2527,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, KnownZeroLow = std::min(KnownZeroLow, KnownZero2.countTrailingOnes()); - if (Opcode == ISD::ADD) { + if (Opcode == ISD::ADD || Opcode == ISD::ADDC) { KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroLow); if (KnownZeroHigh > 1) KnownZero |= APInt::getHighBitsSet(BitWidth, KnownZeroHigh - 1); @@ -2945,6 +2946,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const { } break; case ISD::ADD: + case ISD::ADDC: // Add can have at most one carry bit. Thus we know that the output // is, at worst, one more bit than the inputs. Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); diff --git a/llvm/test/CodeGen/X86/known-bits.ll b/llvm/test/CodeGen/X86/known-bits.ll index cd39b441a0e..f3fa12700f9 100644 --- a/llvm/test/CodeGen/X86/known-bits.ll +++ b/llvm/test/CodeGen/X86/known-bits.ll @@ -138,10 +138,9 @@ define i128 @knownbits_mask_addc_shl(i64 %a0, i64 %a1, i64 %a2) nounwind { ; X32-NEXT: adcl $0, %ecx ; X32-NEXT: shldl $22, %edx, %ecx ; X32-NEXT: shldl $22, %esi, %edx -; X32-NEXT: shll $22, %esi -; X32-NEXT: movl %esi, 4(%eax) ; X32-NEXT: movl %edx, 8(%eax) ; X32-NEXT: movl %ecx, 12(%eax) +; X32-NEXT: movl $0, 4(%eax) ; X32-NEXT: movl $0, (%eax) ; X32-NEXT: popl %esi ; X32-NEXT: popl %edi @@ -155,8 +154,7 @@ define i128 @knownbits_mask_addc_shl(i64 %a0, i64 %a1, i64 %a2) nounwind { ; X64-NEXT: sbbq %rax, %rax ; X64-NEXT: subl %eax, %edx ; X64-NEXT: shldq $54, %rsi, %rdx -; X64-NEXT: shlq $54, %rsi -; X64-NEXT: movq %rsi, %rax +; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq %1 = and i64 %a0, -1024 %2 = zext i64 %1 to i128 |
