diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/vector-align.ll | 38 |
2 files changed, 45 insertions, 7 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 34b03fb74ce..4d7a1f4a6bf 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -121,19 +121,19 @@ namespace llvm { FunctionPass *createHexagonStoreWidening(); } // end namespace llvm; -/// HexagonTargetMachine ctor - Create an ILP32 architecture model. -/// -/// Hexagon_TODO: Do I need an aggregate alignment? -/// HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : LLVMTargetMachine(T, "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-" - "i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-" - "n16:32", TT, CPU, FS, Options, RM, CM, OL), + // Specify the vector alignment explicitly. For v512x1, the calculated + // alignment would be 512*alignment(i1), which is 512 bytes, instead of + // the required minimum of 64 bytes. + : LLVMTargetMachine(T, "e-m:e-p:32:32:32-a:0-n16:32-" + "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" + "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048", + TT, CPU, FS, Options, RM, CM, OL), TLOF(make_unique<HexagonTargetObjectFile>()) { initAsmInfo(); } diff --git a/llvm/test/CodeGen/Hexagon/vector-align.ll b/llvm/test/CodeGen/Hexagon/vector-align.ll new file mode 100644 index 00000000000..557ee3f97f2 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/vector-align.ll @@ -0,0 +1,38 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \ +; RUN: | FileCheck %s + +; Check that the store to Q6VecPredResult does not get expanded into multiple +; stores. There should be no memd's. This relies on the alignment specified +; in the data layout string, so don't provide one here to make sure that the +; default one from HexagonTargetMachine is correct. + +; CHECK-NOT: memd + + +@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64 + +; Function Attrs: nounwind +define i32 @foo() #0 { +entry: + %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) + %1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 -2147483648) + store <512 x i1> %1, <512 x i1>* bitcast (<16 x i32>* @Q6VecPredResult to <512 x i1>*), align 64, !tbaa !1 + tail call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 + ret i32 0 +} + +; Function Attrs: nounwind readnone +declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 + +; Function Attrs: nounwind readnone +declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 + +declare void @print_vecpred(i32, i8*) #2 + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } + +!1 = !{!2, !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} |
