diff options
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsHexagon.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonIntrinsics.td | 17 |
2 files changed, 17 insertions, 2 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsHexagon.td b/llvm/include/llvm/IR/IntrinsicsHexagon.td index bdc82d19e9f..6519f051dee 100644 --- a/llvm/include/llvm/IR/IntrinsicsHexagon.td +++ b/llvm/include/llvm/IR/IntrinsicsHexagon.td @@ -2998,7 +2998,7 @@ Hexagon_di_di_Intrinsic<"HEXAGON_A2_tfrp">; // BUILTIN_INFO(HEXAGON.A2_tfrpi,DI_ftype_SI,1) // def int_hexagon_A2_tfrpi : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_tfrpi">; +Hexagon_di_si_Intrinsic<"HEXAGON_A2_tfrpi">; // // BUILTIN_INFO(HEXAGON.A2_zxtb,SI_ftype_SI,1) // diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index 0ec0a44df65..a319dd4f978 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -744,7 +744,22 @@ def : Pat <(int_hexagon_A2_tfrih I32:$Rs, u16_0ImmPred:$Is), // Transfer Register/immediate. def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>; def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>; -def : T_I_pat <A2_tfrpi, int_hexagon_A2_tfrpi>; + +def ImmExt64: SDNodeXForm<imm, [{ + int64_t V = N->getSExtValue(); + return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i64); +}]>; + +// A2_tfrpi has an operand of type i64. This is necessary, since it is +// generated from "(set I64:$Rd, imm)". That pattern would not appear +// in the DAG, if the immediate was not a 64-bit value. +// The builtin for A2_tfrpi, on the other hand, takes a 32-bit value, +// which makes it impossible to simply replace it with the instruction. +// To connect the builtin with the instruction, the builtin's operand +// needs to be extended to the right type. + +def : Pat<(int_hexagon_A2_tfrpi imm:$Is), + (A2_tfrpi (ImmExt64 $Is))>; // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32) def : Pat<(int_hexagon_A2_tfrp I64:$src), |
