diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pr38533.ll | 19 |
2 files changed, 21 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index fc14f41845c..432f4c6a4f2 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -269,8 +269,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); case TargetLowering::TypePromoteFloat: { // Convert the promoted float by hand. - SDValue PromotedOp = GetPromotedFloat(InOp); - return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); + if (!NOutVT.isVector()) + return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); break; } case TargetLowering::TypeExpandInteger: diff --git a/llvm/test/CodeGen/X86/pr38533.ll b/llvm/test/CodeGen/X86/pr38533.ll index 4c57d84fe65..d6429b7a1fa 100644 --- a/llvm/test/CodeGen/X86/pr38533.ll +++ b/llvm/test/CodeGen/X86/pr38533.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s +; This test makes sure that a vector that needs to be promoted that is bitcasted to fp16 is legalized correctly without causing a width mismatch. define void @constant_fold_vector_to_half() { ; CHECK-LABEL: constant_fold_vector_to_half: ; CHECK: # %bb.0: @@ -9,3 +10,21 @@ define void @constant_fold_vector_to_half() { store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef ret void } + +; Similarly this makes sure that the opposite bitcast of the above is also legalized without crashing. +define void @pr38533_2(half %x) { +; CHECK-LABEL: pr38533_2: +; CHECK: # %bb.0: +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: callq __gnu_f2h_ieee +; CHECK-NEXT: movw %ax, {{[0-9]+}}(%rsp) +; CHECK-NEXT: movzwl {{[0-9]+}}(%rsp), %eax +; CHECK-NEXT: movw %ax, (%rax) +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: retq + %a = bitcast half %x to <4 x i4> + store volatile <4 x i4> %a, <4 x i4>* undef + ret void +} |
