diff options
4 files changed, 156 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index 01dfd4dc195..247d3bfd044 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -54,6 +54,10 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { {s32, p0, 16, 8}}) .minScalar(0, s32); + getActionDefinitionsBuilder({G_ZEXT, G_SEXT}) + .legalIf([](const LegalityQuery &Query) { return false; }) + .maxScalar(0, s32); + getActionDefinitionsBuilder(G_TRUNC) .legalIf([](const LegalityQuery &Query) { return false; }) .maxScalar(1, s32); diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir new file mode 100644 index 00000000000..2e19ed2987b --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir @@ -0,0 +1,61 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + define void @zext() {entry: ret void} + define void @sext() {entry: ret void} + +... +--- +name: zext +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: zext + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) + ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) + ; MIPS32: $v0 = COPY [[UV]](s32) + ; MIPS32: $v1 = COPY [[UV1]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1 + %0:_(s32) = COPY $a0 + %1:_(s64) = G_ZEXT %0(s32) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $v0 = COPY %2(s32) + $v1 = COPY %3(s32) + RetRA implicit $v0, implicit $v1 + +... +--- +name: sext +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: sext + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) + ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32) + ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32) + ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) + ; MIPS32: $v0 = COPY [[UV]](s32) + ; MIPS32: $v1 = COPY [[UV1]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1 + %0:_(s32) = COPY $a0 + %1:_(s64) = G_SEXT %0(s32) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $v0 = COPY %2(s32) + $v1 = COPY %3(s32) + RetRA implicit $v0, implicit $v1 + +... diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll new file mode 100644 index 00000000000..1249d5c9554 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 + +define i64 @zext(i32 %x) { +; MIPS32-LABEL: zext: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: ori $3, $zero, 0 +; MIPS32-NEXT: move $2, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %conv = zext i32 %x to i64 + ret i64 %conv +} + +define i64 @sext(i32 %x) { +; MIPS32-LABEL: sext: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: ori $1, $zero, 31 +; MIPS32-NEXT: srav $3, $4, $1 +; MIPS32-NEXT: move $2, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %conv = sext i32 %x to i64 + ret i64 %conv +} diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir new file mode 100644 index 00000000000..149219acd7e --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir @@ -0,0 +1,64 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + define void @zext() {entry: ret void} + define void @sext() {entry: ret void} + +... +--- +name: zext +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: zext + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 + ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; MIPS32: $v0 = COPY [[COPY]](s32) + ; MIPS32: $v1 = COPY [[C]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1 + %0:_(s32) = COPY $a0 + %4:_(s32) = G_CONSTANT i32 0 + %1:_(s64) = G_MERGE_VALUES %0(s32), %4(s32) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $v0 = COPY %2(s32) + $v1 = COPY %3(s32) + RetRA implicit $v0, implicit $v1 + +... +--- +name: sext +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0 + + ; MIPS32-LABEL: name: sext + ; MIPS32: liveins: $a0 + ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 + ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31 + ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32) + ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]](s32) + ; MIPS32: $v0 = COPY [[COPY]](s32) + ; MIPS32: $v1 = COPY [[ASHR]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1 + %0:_(s32) = COPY $a0 + %7:_(s32) = G_CONSTANT i32 31 + %8:_(s32) = G_CONSTANT i32 0 + %6:_(s32) = COPY %7(s32) + %5:_(s32) = G_ASHR %0, %6(s32) + %1:_(s64) = G_MERGE_VALUES %0(s32), %5(s32) + %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) + $v0 = COPY %2(s32) + $v1 = COPY %3(s32) + RetRA implicit $v0, implicit $v1 + +... |
