diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 4 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/sopk.s | 12 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/sopk_vi.txt | 4 |
3 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 7b8a62bc8fb..f33d412ba68 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -423,13 +423,13 @@ defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>; defm S_SETREG_B32 : SOPK_m < sopk<0x13, 0x12>, "s_setreg_b32", (outs), - (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16" + (ins SReg_32:$sdst, u16imm:$simm16), " $simm16, $sdst" >; // FIXME: Not on SI? //defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>; defm S_SETREG_IMM32_B32 : SOPK_IMM32 < sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs), - (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16" + (ins i32imm:$imm, u16imm:$simm16), " $simm16, $imm" >; //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/AMDGPU/sopk.s b/llvm/test/MC/AMDGPU/sopk.s index 549708b057d..d3670752e62 100644 --- a/llvm/test/MC/AMDGPU/sopk.s +++ b/llvm/test/MC/AMDGPU/sopk.s @@ -77,10 +77,10 @@ s_getreg_b32 s2, 0x6 // SICI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9] // VI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8] -s_setreg_b32 s2, 0x6 -// SICI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb9] -// VI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9] +s_setreg_b32 0x6, s2 +// SICI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x82,0xb9] +// VI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9] -s_setreg_imm32_b32 0xff, 0x6 -// SICI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00] -// VI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] +s_setreg_imm32_b32 0x6, 0xff +// SICI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00] +// VI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/sopk_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/sopk_vi.txt index a0777afd3e4..10767dad0b6 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/sopk_vi.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/sopk_vi.txt @@ -51,8 +51,8 @@ # VI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8] 0x06 0x00 0x82 0xb8 -# VI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9] +# VI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9] 0x06 0x00 0x02 0xb9 -# VI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] +# VI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00] 0x06 0x00 0x00 0xba 0xff 0x00 0x00 0x00 |
