diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx-schedule.ll | 4 |
2 files changed, 13 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 9dcc968a1a7..40e7345cdd2 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -462,5 +462,16 @@ def WriteVSQRTYPSLd: SchedWriteRes<[JLAGU, JFPU1]> { } def : InstRW<[WriteVSQRTYPSLd], (instregex "VSQRTPSYm")>; +def WriteJVZEROALL: SchedWriteRes<[]> { + let Latency = 90; + let NumMicroOps = 73; +} +def : InstRW<[WriteJVZEROALL], (instregex "VZEROALL")>; + +def WriteJVZEROUPPER: SchedWriteRes<[]> { + let Latency = 46; + let NumMicroOps = 37; +} +def : InstRW<[WriteJVZEROUPPER], (instregex "VZEROUPPER")>; } // SchedModel diff --git a/llvm/test/CodeGen/X86/avx-schedule.ll b/llvm/test/CodeGen/X86/avx-schedule.ll index 52506bf5af1..88b810262c6 100644 --- a/llvm/test/CodeGen/X86/avx-schedule.ll +++ b/llvm/test/CodeGen/X86/avx-schedule.ll @@ -2850,7 +2850,7 @@ define void @test_zeroall() { ; ; BTVER2-LABEL: test_zeroall: ; BTVER2: # BB#0: -; BTVER2-NEXT: vzeroall +; BTVER2-NEXT: vzeroall # sched: [90:?] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_zeroall: @@ -2875,7 +2875,7 @@ define void @test_zeroupper() { ; ; BTVER2-LABEL: test_zeroupper: ; BTVER2: # BB#0: -; BTVER2-NEXT: vzeroupper +; BTVER2-NEXT: vzeroupper # sched: [46:?] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_zeroupper: |
