diff options
| -rw-r--r-- | llvm/lib/Target/Mips/Mips16InstrInfo.h | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips16RegisterInfo.h | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFormats.td | 2 |
4 files changed, 14 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.h b/llvm/lib/Target/Mips/Mips16InstrInfo.h index 16487e7937e..3704e2573f4 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.h +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.h @@ -96,8 +96,9 @@ private: unsigned Reg1, unsigned Reg2) const; // Adjust SP by Amount bytes where bytes can be up to 32bit number. - void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const; + void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; }; diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.h b/llvm/lib/Target/Mips/Mips16RegisterInfo.h index ba0d25d5b0e..61017396374 100644 --- a/llvm/lib/Target/Mips/Mips16RegisterInfo.h +++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.h @@ -22,7 +22,8 @@ class Mips16InstrInfo; class Mips16RegisterInfo : public MipsRegisterInfo { const Mips16InstrInfo &TII; public: - Mips16RegisterInfo(const MipsSubtarget &Subtarget, const Mips16InstrInfo &TII); + Mips16RegisterInfo(const MipsSubtarget &Subtarget, + const Mips16InstrInfo &TII); void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 3961dd63b2c..d1f4458233d 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -330,8 +330,12 @@ def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; -def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; -def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; -def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; -def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; +def : InstAlias<"dmfc0 $rt, $rd", + (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; +def : InstAlias<"dmtc0 $rt, $rd", + (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; +def : InstAlias<"dmfc2 $rt, $rd", + (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; +def : InstAlias<"dmtc2 $rt, $rd", + (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td index b9f24b82c5f..c026b5dae03 100644 --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -173,7 +173,7 @@ class FJ<bits<6> op> let Inst{25-0} = target; } - //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> //===----------------------------------------------------------------------===// class MFC3OP_FM<bits<6> op, bits<5> mfmt> |
