diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 48 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll | 35 |
2 files changed, 83 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index b323e78cfab..f4e0cb7fd13 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -484,6 +484,54 @@ def GR64_ : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> { // of registers which do not by themselves require a REX prefix. def GR8_NOREX : RegisterClass<"X86", [i8], 8, [AL, CL, DL, SIL, DIL, BL, BPL, SPL]> { + let MethodProtos = [{ + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + // Does the function dedicate RBP / EBP to being a frame ptr? + // If so, don't allocate SPL or BPL. + static const unsigned X86_GR8_NOREX_AO_64_fp[] = { + X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL + }; + // If not, just don't allocate SPL. + static const unsigned X86_GR8_NOREX_AO_64[] = { + X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL + }; + // In 32-mode, none of the 8-bit registers aliases EBP or ESP. + static const unsigned X86_GR8_NOREX_AO_32[] = { + X86::AL, X86::CL, X86::DL, X86::BL + }; + + GR8_NOREXClass::iterator + GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); + const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); + if (!Subtarget.is64Bit()) + return X86_GR8_NOREX_AO_32; + else if (RI->hasFP(MF)) + return X86_GR8_NOREX_AO_64_fp; + else + return X86_GR8_NOREX_AO_64; + } + + GR8_NOREXClass::iterator + GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); + const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); + if (!Subtarget.is64Bit()) + return X86_GR8_NOREX_AO_32 + + (sizeof(X86_GR8_NOREX_AO_32) / sizeof(unsigned)); + else if (RI->hasFP(MF)) + return X86_GR8_NOREX_AO_64_fp + + (sizeof(X86_GR8_NOREX_AO_64_fp) / sizeof(unsigned)); + else + return X86_GR8_NOREX_AO_64 + + (sizeof(X86_GR8_NOREX_AO_64) / sizeof(unsigned)); + } + }]; } def GR16_NOREX : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> { diff --git a/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll new file mode 100644 index 00000000000..5dda4e9ec0f --- /dev/null +++ b/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll @@ -0,0 +1,35 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast -regalloc=local | not grep sil +; rdar://6787136 + + %struct.X = type { i8, [32 x i8] } +@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @z to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define i32 @z() nounwind ssp { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %xxx = alloca %struct.X ; <%struct.X*> [#uses=6] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %1 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1] + %2 = getelementptr [32 x i8]* %1, i32 0, i32 31 ; <i8*> [#uses=1] + store i8 48, i8* %2, align 1 + %3 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1] + %4 = getelementptr [32 x i8]* %3, i32 0, i32 31 ; <i8*> [#uses=1] + %5 = load i8* %4, align 1 ; <i8> [#uses=1] + %6 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1] + %7 = getelementptr [32 x i8]* %6, i32 0, i32 0 ; <i8*> [#uses=1] + store i8 %5, i8* %7, align 1 + %8 = getelementptr %struct.X* %xxx, i32 0, i32 0 ; <i8*> [#uses=1] + store i8 15, i8* %8, align 1 + %9 = call i32 (...)* bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval align 4 %xxx, %struct.X* byval align 4 %xxx) nounwind ; <i32> [#uses=1] + store i32 %9, i32* %0, align 4 + %10 = load i32* %0, align 4 ; <i32> [#uses=1] + store i32 %10, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval1 +} + +declare i32 @f(%struct.X* byval align 4, %struct.X* byval align 4) nounwind ssp |
